Conferences in DBLP
Xiang-Dong Tan , C.-J. Richard Shi Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Youcef Bourai , C.-J. Richard Shi Symmetry Detection for Automatic Analog-Layout Recycling. [Citation Graph (0, 0)][DBLP ] Conf ] Huazhong Yang , Rong Luo , Hui Wang , Runsheng Liu An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Tianming Kong , Dongmin Xu , Faming Liang , Jun S. Liu , Wing Hung Wong Relaxed Simulated Tempering for VLSI Floorplan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Fung Yu Young , D. F. Wong Slicing Floorplans with Boundary Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaohai Wu , Changge Qiao , Xianlong Hong Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Ju-Hyung Kim , Sung-Wook Hwang , Seung-Hoon Lee , Yong Jee An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Byeong-Lyeol Jeon , Kang-Jin Lee , Seung-Hoon Lee , Sang-Won Yoon A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Byung-Soo Choi , Dong-Wook Lee , Dong-Ik Lee The Design of Delay Insensitive Asynchronous 16-bit Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Shin'ichi Wakabayashi , Tetsushi Koide , Naoyoshi Toshine , Mutsuaki Goto , Yoshikatsu Nakayama , Koichi Hatta An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Li Jiang , Dongju Li , Shintaro Haba , Chawalit Honsawek , Hiroaki Kunieda Motion Estimator LSI for MPEG2 High Level Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Kug Lee , Dong-Young Chang , Geun-Soon Kang , Seung-Hoon Lee A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC. [Citation Graph (0, 0)][DBLP ] Conf ] Tae Hun Kim , Jeongsik Yang , Kyoo Hyun Lim , Jin Wook Kim , Jeong Eun Lee , Hyoung Sik Nam , Young Gon Kim , Jeong Pyo Kim , Sang Lin Byun , Bae Sung Kwon , Beomsup Kim 16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury Reduced-Order Modelling of Time-Varying Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Onuttom Narayan , Jaijeet S. Roychowdhury Analysing Forced Oscillators with Multiple Time Scales. [Citation Graph (0, 0)][DBLP ] Conf ] Yao-Lin Jiang , Omar Wing Waveform Relaxation of Linear Integral-Differential Equations for Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark M. Gourary , Sergey G. Rusakov , Sergey L. Ulyanov , Michael M. Zharov , Kiran K. Gullapalli , Brian J. Mulvaney A New Technique to Exploit Frequency Domain Latency in Harmonic Balance Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Jong-Sheng Cherng , Sao-Jie Chen , Chia-Chun Tsai , Jan-Ming Ho An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] C. K. Eem , J. W. Chong An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Shiuann-Shiuh Lin , Wen-Hsin Chen , Wen-Wei Lin , TingTing Hwang A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jan-Yang Chang , Yu-Chen Liu , Ting-Chi Wang Faster and Better Spectral Algorithms for Multi-Way Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Takahashi , Kimihiro Ogawa , Kenneth S. Kundert VCO Jitter Simulation and Its Comparison With Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Zheng , Wenjun Zhang , Lilin Tian , Zhilian Yang Enhancing the Efficiency of Reduction of Large RC networks By Pole Analysis via Congruence Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Jinsong Hou , Zeyi Wang , Xianlong Hong The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , David Zhigang Pan Interconnect Delay Estimation Models for Synthesis and Design Planning. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Zhou , Zhijun Huang , Jiarong Tong , Pushan Tang An Analytical Delay Model for SRAM-Based FPGA Interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Shihliang Ou , Massoud Pedram Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Massoud Pedram , Chi-Ying Tsui , Qing Wu An Integrated Battery-Hardware Model for Portable Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Shinichiro Mutoh , Satoshi Shigematsu , Yoshinori Gotoh , Shinsuke Konaka Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Su Kwon , Bong-Il Park , In-Cheol Park , Chong-Min Kyung A New Single-Clock Flip-Clop for Half-Swing Clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Y. Yun , Ayoob E. Dooply Optimal Evaluation Clocking of Self-Resetting Domino Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoyuki Yoda , Atsushi Takahashi , Yoji Kajitani Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Dongsheng Wang , Ping Zhang , Chung-Kuan Cheng , Arunabha Sen A Performance-Driven I/O Pin Routing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Shuenn-Shi Chen , Jong-Jang Chen , Sao-Jie Chen , Chia-Chun Tsai An Automatic Router for the Pin Grid Array Package. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Xiao , Malgorzata Marek-Sadowska Crosstalk Reduction by Transistor Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-chee Wong , Philip C. H. Chan , Wai-on Law A Technology-Independent Methodology of Placement Generation for Analog Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Wei Yeh , Chin-Chao Chang , Jinn-Shyan Wang Technnology Mapping for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Maolin Tang , Kamran Eshraghian , Hon Nin Cheung An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Nagu R. Dhanwada , Adrián Núñez-Aldana , Ranga Vemuri Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Hoon Choi , Hansoo Kim , In-Cheol Park , Seung Ho Hwang , Chong-Min Kyung Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Hidehisa Nagano , Takayuki Suyama , Akira Nagoya Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Mark M. Gourary , Sergey G. Rusakov , Sergey L. Ulyanov , Michael M. Zharov , Brian J. Mulvaney A New Numerical Method for Transient Noise Analysis of Nonlinear Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rung-Bin Lin , Jinq-Chang Chen Low Power CMOS Off-Chip Drivers with Slew-rate Difference. [Citation Graph (0, 0)][DBLP ] Conf ] Rung-Bin Lin , Isaac Shuo-Hsiu Chou , Chi-Ming Tsai Benchmark Circuits Improve the Quality of a Standard Cell Library. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Takenaka , Junji Kitamichi , Teruo Higashino , Kenichi Taniguchi Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution. [Citation Graph (0, 0)][DBLP ] Conf ] Koichi Hatta , Shin'ichi Wakabayashi , Tetsushi Koide Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. [Citation Graph (0, 0)][DBLP ] Conf ] Ren-Der Chen , Jer-Min Jou , Yeu-Horng Shiau Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jiann-Horng Lin , Jing-Yang Jou , Iris Hui-Ru Jiang Hierarchical Floorplan Design on the Internet. [Citation Graph (0, 0)][DBLP ] Conf ] Ryoji Sakurai , Mizuki Takahashi , Andrew Kay , Akihisa Yamada , Tetsuya Fujimoto , Takashi Kambe A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] P. W. Cheng , H. C. Huang Electronics Development of Silicon Microdisplay for Virtual Reality Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Seung-Min Lee , Jin-Hong Chung , Mike Myung-Ok Lee High-Speed and Low-Power Real-Time Programmable Video Multi-Processor for MPEG-2 Multimedia Chip on 0.6µm TLM CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Jer-Min Jou , Pei-Yin Chen , Yeu-Horng Shiau , Ming-Shiang Liang A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Jer-Min Jou , Shiann-Rong Kuang , Yeu-Horng Shiau A New Pipelined Architecture for Fuzzy Color Correction. [Citation Graph (0, 0)][DBLP ] Conf ] Edoardo Charbon , Ilhami Torunoglu Watermarking Layout Topologies. [Citation Graph (0, 0)][DBLP ] Conf ] Youxin Gao , D. F. Wong Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Gabriel Robins , Anish Singh , Alexander Zelikovsky New Multilevel and Hierarchical Algorithms for Layout Density Control. [Citation Graph (0, 0)][DBLP ] Conf ] Ross Baldick , Andrew B. Kahng , Andrew A. Kennings , Igor L. Markov Function Smoothing with Applications to VLSI Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Yun-Yin Lian , Youn-Long Lin Layout-based Logic Decomposition for Timing Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-hong Chen , Chi-Ying Tsui Timing Optimization of Logic Network Using Gate Duplication. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Rabiei , Massoud Pedram Model Order Reduction of Large Circuits Using Balanced Truncation. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Paul Tucker , Alexander Zelikovsky Optimization of Linear Placements for Wirelength Minimization with Free Sites. [Citation Graph (0, 0)][DBLP ] Conf ] Haiyun Bao , Xianlong Hong , Yici Cai A New Global Routing Algorithm Independent Of Net Ordering. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Huang , Xianlong Hong , Changge Qiao , Yici Cai A Timing-Driven Block Placer Based on Sequence Pair Model. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Y. Yun Recent Advances in Asynchronous Design Methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] Jack L. Chan , Steve S. Chung Universal Switched-Current Integrator Blocks for SI Filter Design. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Sung-Dae , Jang Myung-Jun , Leex Won-Hyo An On-Chip Automatic Tuning Circuit using Integration Level Approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Won Hyo Lee , Jun Dong Cho , Sung Dae Lee A High Speed and Low Power Phase-Frequency Detector and Charge - pump. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Kug Lee , Dong-Young Chang , Geun-Soon Kang , Seung-Hoon Lee A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaowei Li , Paul Y. S. Cheung Data Path Synthesis for BIST with Low Area Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Feng Wu , Cheng-Wen Wu Testing Interconnects of Dynamic Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yinlei Yu , Jian Xu , Wei-Kang Huang , Fabrizio Lombardi Diagnosing Single Faults for Interconnects in SRAM Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Hafizur Rahaman , Debesh K. Das , Bhargab B. Bhattacharya An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Zhang , Tsuyoshi Shinogi , Haruhiko Takase , Terumine Hayashi A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. [Citation Graph (0, 0)][DBLP ] Conf ] Toshio Murayama , Kimihiro Ogawa , Haruhiko Yamaguchi Estimation of Peak Current through CMOS VLSI Circuit Supply Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Yibin Ye , Kaushik Roy , Rolf Drechsler Power Consumption in XOR-Based Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Nicole Drechsler Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Keung Lo , Philip C. H. Chan An Efficient Structural Approach to Board Interconnect Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Ding , Yu-Liang Wu On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Keim , Nicole Drechsler , Bernd Becker Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Junji Kitamichi , Hiroyuki Kageyama , Nobuo Funabiki Formal Verification Method for Combinatorial Circuits at High Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Günther , Rolf Drechsler Minimization of Free BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Meinel , Klaus Schwettmann , Anna Slobodová Application Driven Variable Reordering and an Example Implementation in Reachability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Yukihiro Iguchi , Munehiro Matsuura , Tsutomu Sasao , Atsumu Iseno Realization of Regular Ternary Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Nozomu Togawa , Takashi Sakurai , Masao Yanagisawa , Tatsuo Ohtsuki A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Leupers , Johann Elste , Birger Landwehr Generation of Interpretive and Compiled Instruction Set Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos A. Kountouris , Christophe Wolinski Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors. [Citation Graph (0, 0)][DBLP ] Conf ] Marcello Lajolo , Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Jong Fang , Peng-Cheng Kao , Allen C.-H. Wu A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Birger Landwehr A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Debatosh Debnath , Tsutomu Sasao Fast Boolean Matching Under Permutation Using Representative. [Citation Graph (0, 0)][DBLP ] Conf ] Jinsong Bei , Hongxing Li , Jinian Bian , Hongxi Xue , Xianlong Hong FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] 