The SCEAS System
Navigation Menu

Conferences in DBLP

Asia-Pacific Computer Systems Architecture Conference (ACSAC) (aPcsac)
2006 (conf/aPcsac/2006)

  1. Guang R. Gao
    The Era of Multi-core Chips -A Fresh Look on Software Challenges. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:1- [Conf]
  2. Alexander V. Shafarenko
    Streaming Networks for Coordinating Data-Parallel Programs (Position Statement). [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:2-5 [Conf]
  3. Mariusz Bajger, Amos Omondi
    Implementations of Square-Root and Exponential Functions for Large FPGAs. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:6-23 [Conf]
  4. Sung Woo Chung, Kevin Skadron
    Using Branch Prediction Information for Near-Optimal I-Cache Leakage. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:24-37 [Conf]
  5. Jing Du, Xuejun Yang, Guibin Wang, Fujiang Ao
    Scientific Computing Applications on the Imagine Stream Processor. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:38-51 [Conf]
  6. Haakon Dybdahl, Per Stenström
    Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:52-66 [Conf]
  7. Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
    A Study of the Performance Potential for Dynamic Instruction Hints Selection. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:67-80 [Conf]
  8. Jorrit N. Herder, Herbert Bos, Ben Gras, Philip Homburg, Andrew S. Tanenbaum
    Reorganizing UNIX for Reliability. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:81-94 [Conf]
  9. Ching-Hsien Hsu, Ming-Yuan Own, Kuan-Ching Li
    Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid Computing. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:95-108 [Conf]
  10. Dandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu
    Processor Directed Dynamic Page Policy. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:109-122 [Conf]
  11. Huizhan Yi, Juan Chen, Xuejun Yang
    Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:123-136 [Conf]
  12. Hae-Duck Joshua Jeong, Jong-Suk Ruth Lee
    A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:137-146 [Conf]
  13. Chris R. Jesshope
    muTC - An Intermediate Language for Programming Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:147-160 [Conf]
  14. Lih Wen Koh, Oliver Diessel
    Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:161-174 [Conf]
  15. Lian Li 0002, Jingling Xue
    Trace-Based Data Cache Leakage Reduction at Link Time. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:175-188 [Conf]
  16. Shih-wei Liao
    Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:189-202 [Conf]
  17. Luke Macpherson
    Overload Protection for Commodity Network Appliances. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:203-218 [Conf]
  18. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue
    An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:219-230 [Conf]
  19. Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsunori Kubo
    A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:231-243 [Conf]
  20. Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou
    Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:244-259 [Conf]
  21. Feilong Tang, Minglu Li, Chuliang Weng, Chongqing Zhang, Wenzhe Zhang, Hongyu Huang, Yi Wang
    Combining Wireless Sensor Network with Grid for Intelligent City Traffic. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:260-269 [Conf]
  22. Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova
    A Novel Processor Architecture for Real-Time Control. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:270-280 [Conf]
  23. Jun Xia, Li Luo, Xuejun Yang
    A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:281-294 [Conf]
  24. Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil
    Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:295-308 [Conf]
  25. Takashi Yokota, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba
    Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:309-322 [Conf]
  26. Ming Z. Zhang, Li Tao, Ming-Jung Seow, Vijayan K. Asari
    Design of an Efficient Flexible Architecture for Color Image Enhancement. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:323-336 [Conf]
  27. Yawen Chen, Hong Shen, Haibo Zhang
    Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:337-343 [Conf]
  28. Yong-ran Chen, Xing-yun Qi, Yue Qian, Wen-hua Dou
    PMPS(3): A Performance Model of Parallel Systems. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:344-350 [Conf]
  29. Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu
    Issues and Support for Dynamic Register Allocation. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:351-358 [Conf]
  30. Jianjun Guo, Kui Dai, Zhiying Wang
    A Heterogeneous Multi-core Processor Architecture for High Performance Computing. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:359-365 [Conf]
  31. Michael Hicks 0002, Colin Egan, Bruce Christianson, Patrick Quick
    Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:366-372 [Conf]
  32. Sun-Yuan Hsieh
    Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:373-379 [Conf]
  33. Hsien-Jone Hsieh, Dyi-Rong Duh
    Constructing Node-Disjoint Paths in Enhanced Pyramid Networks. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:380-386 [Conf]
  34. Sheng-Kai Hung, Yarsun Hsu
    Striping Cache: A Global Cache for Striped Network File System. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:387-393 [Conf]
  35. Yi Jiang, Guangtao Xue, Minglu Li, Jinyuan You
    DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:394-400 [Conf]
  36. Zhentao Li, Shuming Chen, Zhaoliang Li, Conghua Lei
    The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:401-408 [Conf]
  37. Peng Li, Dongsheng Wang, Songliu Guo, Tao Tian, Weimin Zheng
    Live Range Aware Cache Architecture. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:409-415 [Conf]
  38. Jason M. McGuiness, Colin Egan, Bruce Christianson, Guang Gao
    The Challenges of Efficient Code-Generation for Massively Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:416-422 [Conf]
  39. Kunio Okuda, Siang Wun Song, Marcos Tatsuo Yamamoto
    Reliable Systolic Computing Through Redundancy. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:423-429 [Conf]
  40. Yantao Pan, Xicheng Lu, Peidong Zhu, Shen Ma
    A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:430-436 [Conf]
  41. Biju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan
    A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:437-444 [Conf]
  42. Soong Hyun Shin, Sung Woo Chung, Chu Shik Jhon
    On the Reliability of Drowsy Instruction Caches. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:445-451 [Conf]
  43. Kang Sun, Lingdi Ping, Jiebing Wang, Zugen Liu, Xuezeng Pan
    Design of a Reconfigurable Cryptographic Engine. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:452-458 [Conf]
  44. Caixia Sun, Hongwei Tang, Minxuan Zhang
    Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:459-465 [Conf]
  45. Himanshu Thapliyal, M. B. Srinivas
    The New BCD Subtractor and Its Reversible Logic Implementation. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:466-472 [Conf]
  46. Tianzhou Chen, Wei Hu, Yi Lian
    Power-Efficient Microkernel of Embedded Operating System on Chip. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:473-479 [Conf]
  47. Lucian N. Vintan, Arpad Gellert, Adrian Florea, Marius Oancea, Colin Egan
    Understanding Prediction Limits Through Unbiased Branches. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:480-487 [Conf]
  48. Dong Wang, Xiao Hu, Shuming Chen, Yang Guo
    Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:488-494 [Conf]
  49. Wang Lei, Zhiping Chen
    Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:495-501 [Conf]
  50. Lei Wang, Zhiying Wang, Kui Dai
    Cycle Period Analysis and Optimization of Timed Circuits. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:502-508 [Conf]
  51. Haixia Wang, Dongsheng Wang, Peng Li
    Acceleration Techniques for Chip-Multiprocessor Simulator Debug. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:509-515 [Conf]
  52. Meiling Wang, Lei Liu
    A DDL-Based Software Architecture Model. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:516-522 [Conf]
  53. Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen
    Branch Behavior Characterization for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:523-530 [Conf]
  54. Mei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang
    Optimization and Evaluating of StreamYGX2 on MASA Stream Processor. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:531-537 [Conf]
  55. Kenneth M. Wilson, Philip Machanick
    SecureTorrent: A Security Framework for File Swarming. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:538-544 [Conf]
  56. Nan Wu, Mei Wen, Ju Ren, Yi He, Chunyuan Zhang
    Register Allocation on Stream Processor with Local Register File. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:545-551 [Conf]
  57. Xiaofeng Wu, Tanya Vladimirova
    A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:552-558 [Conf]
  58. Xiao-Bo Yan, Xue-Jun Yang, Pu Wen
    Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:559-566 [Conf]
  59. Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong
    Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:567-573 [Conf]
  60. Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim
    Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:574-580 [Conf]
  61. ChangRyul Yun, YoungHwan Bae, HanJin Cho, KyoungSon Jhang
    Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:581-587 [Conf]
  62. Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing
    An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:588-594 [Conf]
  63. Wenhong Zhao, Feng Xia
    An Efficient Approach to Energy Saving in Microcontrollers. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:595-601 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002