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Asia and South Pacific Design Automation Conference (ASP-DAC) (aspdac)
2006 (conf/aspdac/2006)

  1. Satoru Ito
    Challenging device innovation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:- [Conf]
  2. Yukichi Niwa
    Effective platform-based development for large-scale systems design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:- [Conf]
  3. Alberto L. Sangiovanni-Vincentelli
    Automotive electronics: steady growth for years to come! [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:- [Conf]
  4. Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    Transition-based coverage estimation for symbolic model checking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:1-6 [Conf]
  5. Bijan Alizadeh
    Word level functional coverage computation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:7-12 [Conf]
  6. Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti
    Discovering the input assumptions in specification refinement coverage. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:13-18 [Conf]
  7. Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah
    Refinement strategies for verification methods based on datapath abstraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:19-24 [Conf]
  8. Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
    Generation of shorter sequences for high resolution error diagnosis using sequential SAT. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:25-29 [Conf]
  9. Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
    Constraint-driven bus matrix synthesis for MPSoC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:30-35 [Conf]
  10. Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz
    Improving routing efficiency for network-on-chip through contention-aware input selection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:36-41 [Conf]
  11. Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor
    Physical design implementation of segmented buses to reduce communication energy. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:42-47 [Conf]
  12. Mário P. Véstias, Horácio C. Neto
    Co-synthesis of a configurable SoC platform based on a network on chip architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:48-53 [Conf]
  13. Muhammad Omer Cheema, Omar Hammami
    Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:54-60 [Conf]
  14. Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan
    Robust analytical gate delay modeling for low voltage circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:61-66 [Conf]
  15. Shahin Nazarian, Massoud Pedram, Tao Lin, Emre Tuncer
    CGTA: current gain-based timing analysis for logic cells. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:67-72 [Conf]
  16. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton
    Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:73-78 [Conf]
  17. Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma
    Crosstalk analysis using reconvergence correlation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:79-83 [Conf]
  18. Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
    Process-induced skew reduction in nominal zero-skew clock trees. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:84-89 [Conf]
  19. Tadayoshi Enomoto, Nobuaki Kobayashi
    A low dynamic power and low leakage power 90-nm CMOS square-root circuit. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:90-91 [Conf]
  20. Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi
    A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:92-93 [Conf]
  21. Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Richard B. Brown
    A 16-bit, low-power microsystem with monolithic MEMS-LC clocking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:94-95 [Conf]
  22. Chi-Ying Tsui, Hui Shao, Wing-Hung Ki, Feng Su
    Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:96-97 [Conf]
  23. Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai
    A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:98-99 [Conf]
  24. Fangqing Chu, Wei Li, Junyan Ren
    An implementation of a CMOS down-conversion mixer for GSM1900 receiver. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:100-101 [Conf]
  25. Yat-Hei Lam, Suet-Chui Koon, Wing-Hung Ki, Chi-Ying Tsui
    Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:102-103 [Conf]
  26. Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui
    Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:104-105 [Conf]
  27. Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki
    A built-in power supply noise probe for digital LSIs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:106-107 [Conf]
  28. Minoru Watanabe, Fuminori Kobayashi
    A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:108-109 [Conf]
  29. Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
    Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:110-111 [Conf]
  30. Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto
    High-throughput decoder for low-density parity-check code. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:112-113 [Conf]
  31. Nursani Rahmatullah, Arif E. Nugroho
    Hardware implementation of super minimum all digital FM demodulator. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:114-115 [Conf]
  32. Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski
    Designing a custom architecture for DCT using NISC technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:116-117 [Conf]
  33. Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
    A 52mW 1200MIPS compact DSP for multi-core media SoC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:118-119 [Conf]
  34. Suh Ho Lee, Ji Hwan Park, Seon Wook Kim, Sung Jea Ko, Suki Kim
    Implementation of H.264/AVC decoder for mobile video applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:120-121 [Conf]
  35. Min Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan
    A high-performance platform-based SoC for information security. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:122-123 [Conf]
  36. Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi
    Configurable multi-processor architecture and its processor element design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:124-125 [Conf]
  37. Hansu Cho, Samar Abdi, Daniel Gajski
    Design and implementation of transducer for ARM-TMS communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:126-127 [Conf]
  38. Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, Feihui Li
    Energy savings through embedded processing on disk system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:128-133 [Conf]
  39. Guilin Chen, Mahmut T. Kandemir, Feihui Li
    Energy-aware computation duplication for improving reliability in embedded chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:134-139 [Conf]
  40. Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Object duplication for improving reliability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:140-145 [Conf]
  41. Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
    Mapping and configuration methods for multi-use-case networks on chips. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:146-151 [Conf]
  42. Hyeyoung Hwang, Taewook Oh, Hyunuk Jung, Soonhoi Ha
    Conversion of reference C code to dataflow model: H.264 encoder case study. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:152-157 [Conf]
  43. Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:158-163 [Conf]
  44. Robert D. Mullins, Andrew West, Simon W. Moore
    The design and implementation of a low-latency on-chip network. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:164-169 [Conf]
  45. Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
    A near optimal deblocking filter for H.264 advanced video coding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:170-175 [Conf]
  46. K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
    Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:176-181 [Conf]
  47. Ismail Kadayif, Mahmut T. Kandemir, Feihui Li
    Prefetching-aware cache line turnoff for saving leakage energy. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:182-187 [Conf]
  48. Jason Cong, Min Xie
    A robust detailed placement for mixed-size IC designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:188-194 [Conf]
  49. Natarajan Viswanathan, Min Pan, Chris C. N. Chu
    FastPlace 2.0: an efficient analytical placer for mixed-mode designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:195-200 [Conf]
  50. Chanseok Hwang, Massoud Pedram
    Timing-driven placement based on monotone cell ordering constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:201-206 [Conf]
  51. Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He
    Constraint driven I/O planning and placement for chip-package co-design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:207-212 [Conf]
  52. Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang
    Simultaneous block and I/O buffer floorplanning for flip-chip design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:213-218 [Conf]
  53. Yong Zhan, Brent Goplen, Sachin S. Sapatnekar
    Electrothermal analysis and optimization techniques for nanoscale integrated circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:219-222 [Conf]
  54. Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
    Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:223-230 [Conf]
  55. Ja Chun Ku, Yehea I. Ismail
    Area optimization for leakage reduction and thermal stability in nanometer scale technologies. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:231-236 [Conf]
  56. Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
    Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:237-242 [Conf]
  57. Neil Kettle, Andy King
    An anytime symmetry detection algorithm for ROBDDs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:243-248 [Conf]
  58. Ming-Hong Su, Chun-Yao Wang
    High level equivalence symmetric input identification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:249-253 [Conf]
  59. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
    Fast multi-domain clock skew scheduling for peak current reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:254-259 [Conf]
  60. Bakhtiar Affendi Rosdi, Atsushi Takahashi
    Low area pipelined circuits by multi-clock cycle paths and clock scheduling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:260-265 [Conf]
  61. Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi
    A transduction-based framework to synthesize RSFQ circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:266-272 [Conf]
  62. Xiaolue Lai, Jaijeet S. Roychowdhury
    Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomena. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:273-278 [Conf]
  63. Michael S. McCorquodale, James L. McCann, Richard B. Brown
    Newton: a library-based analytical synthesis tool for RF-MEMS resonators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:279-284 [Conf]
  64. Qingqi Dou, Jacob A. Abraham
    Jitter decomposition in ring oscillators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:285-290 [Conf]
  65. Prashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury
    A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:291-296 [Conf]
  66. S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha
    Double edge triggered Feedback Flip-Flop in sub 100NM technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:297-302 [Conf]
  67. Kuang-Yao Lee, Ting-Chi Wang
    Post-routing redundant via insertion for yield/reliability improvement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:303-308 [Conf]
  68. Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar
    Temperature-aware routing in 3D ICs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:309-314 [Conf]
  69. Sebastian Vogel, Martin D. F. Wong
    Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:315-319 [Conf]
  70. Zhuo Li, Weiping Shi
    An O(mn) time algorithm for optimal buffer insertion of nets with m sinks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:320-325 [Conf]
  71. Man Chung Hon
    Spec-based flip-flop and latch repeater planning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:326-331 [Conf]
  72. Sang Lyul Min, Eyee Hyun Nam
    Current trends in flash memory technology: invited paper. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:332-333 [Conf]
  73. Tei-Wei Kuo, Jen-Wei Hsieh, Li-Pin Chang, Yuan-Hao Chang
    Configurability of performance and overheads in flash management. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:334-341 [Conf]
  74. Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi
    Delay defect screening for a 2.16GHz SPARC64 microprocessor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:342-347 [Conf]
  75. Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
    A dynamic test compaction procedure for high-quality path delay testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:348-353 [Conf]
  76. Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang
    Delay variation tolerance for domino circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:354-359 [Conf]
  77. Kai Yang, Kwang-Ting Cheng
    Efficient identification of multi-cycle false path. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:360-365 [Conf]
  78. Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
    IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:366-371 [Conf]
  79. Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Youssef, Xi Chen, Wander O. Cesário, Ahmed Amine Jerraya
    High-level architecture exploration for MPEG4 encoder with custom parameters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:372-377 [Conf]
  80. Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
    Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:378-383 [Conf]
  81. Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang
    An automated design flow for 3D microarchitecture evaluation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:384-389 [Conf]
  82. Ozcan Ozturk, Feng Wang 0004, Mahmut T. Kandemir, Yuan Xie
    Optimal topology exploration for application-specific 3D architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:390-395 [Conf]
  83. Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
    Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:396-401 [Conf]
  84. Zhao Li, C.-J. Richard Shi
    A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:402-407 [Conf]
  85. Kiyotaka Yamamura, Wataru Kuroki
    An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:408-415 [Conf]
  86. Baohua Wang, Pinaki Mazumder
    Optimization of circuit trajectories: an auxiliary network approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:416-421 [Conf]
  87. Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan
    SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:422-427 [Conf]
  88. Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh
    An unconditional stable general operator splitting method for transistor level transient analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:428-433 [Conf]
  89. Michaela Guiney, Eric Leavitt
    An introduction to OpenAccess: an open source data model and API for IC design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:434-436 [Conf]
  90. Yoshio Inoue
    Open access overview "industrial experience". [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:437-438 [Conf]
  91. Hillel Ofek
    EDA vendor adoption. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:439- [Conf]
  92. David A. Papa, Igor L. Markov, Philip Chong
    Utility of the OpenAccess database in academic research. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:440-441 [Conf]
  93. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    Depth-driven verification of simultaneous interfaces. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:442-447 [Conf]
  94. Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
    FSM-based transaction-level functional coverage for interface compliance verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:448-453 [Conf]
  95. Nobuyuki Ohba, Kohji Takano
    Hardware debugging method based on signal transitions and transactions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:454-459 [Conf]
  96. Junghee Lee, Joonhwan Yi
    Cycle error correction in asynchronous clock modeling for cycle-based simulation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:460-465 [Conf]
  97. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
    A fast logic simulator using a look up table cascade emulator. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:466-472 [Conf]
  98. Peng Rong, Massoud Pedram
    Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:473-478 [Conf]
  99. Ernesto Wandeler, Lothar Thiele
    Optimal TDMA time slot and cycle length allocation for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:479-484 [Conf]
  100. Hector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar, Francisco Blasco
    POSIX modeling in SystemC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:485-490 [Conf]
  101. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt
    PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:491-496 [Conf]
  102. Hyunok Oh, Nikil Dutt, Soonhoi Ha
    Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:497-502 [Conf]
  103. Sean X. Shi, David Z. Pan
    Wire sizing with scattering effect for nanoscale interconnection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:503-508 [Conf]
  104. Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan
    Adaptive admittance-based conductor meshing for interconnect analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:509-514 [Conf]
  105. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
    Interconnect RL extraction at a single representative frequency. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:515-520 [Conf]
  106. Mengsheng Zhang, Wenjian Yu, Yu Du, Zeyi Wang
    An efficient algorithm for 3-D reluctance extraction considering high frequency effect. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:521-526 [Conf]
  107. Xiaolue Lai, Jaijeet S. Roychowdhury
    Macromodelling oscillators using Krylov-subspace methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:527-532 [Conf]
  108. Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami
    Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:533-540 [Conf]
  109. Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga
    Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:541-546 [Conf]
  110. Masafumi Onouchi, Tetsuya Yamada, Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine
    A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:547-550 [Conf]
  111. Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
    PowerViP: Soc power estimation framework at transaction level. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:551-558 [Conf]
  112. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:559-564 [Conf]
  113. Hyung-Ock Kim, Youngsoo Shin
    Analysis and optimization of gate leakage current of power gating circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:565-569 [Conf]
  114. Naoaki Ohkubo, Kimiyoshi Usami
    Delay modeling and static timing analysis for MTCMOS circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:570-575 [Conf]
  115. Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
    Switching-activity driven gate sizing and Vth assignment for low power design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:576-581 [Conf]
  116. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
    Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:582-587 [Conf]
  117. Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae
    Reusable component IP design using refinement-based design environment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:588-593 [Conf]
  118. Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:594-599 [Conf]
  119. Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
    A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:600-605 [Conf]
  120. Qubo Hu, Arnout Vandecappelle, Martin Palkovic, Per Gunnar Kjeldsberg, Erik Brockmeyer, Francky Catthoor
    Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:606-611 [Conf]
  121. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
    A novel instruction scratchpad memory optimization method based on concomitance metric. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:612-617 [Conf]
  122. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
    DraXRouter: global routing in X-Architecture with dynamic resource assignment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:618-623 [Conf]
  123. Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiko Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama
    Diagonal routing in high performance microprocessor design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:624-629 [Conf]
  124. Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlong Hong
    CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:630-635 [Conf]
  125. Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin
    A novel framework for multilevel full-chip gridless routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:636-641 [Conf]
  126. Yoichi Tomioka, Atsushi Takahashi
    Monotonic parallel and orthogonal routing for single-layer ball grid array packages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:642-647 [Conf]
  127. X.-L. Huang, J.-L. Huang
    A routability constrained scan chain ordering technique for test power reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:648-652 [Conf]
  128. Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
    FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:653-658 [Conf]
  129. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
    Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:659-664 [Conf]
  130. Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
    Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:665-670 [Conf]
  131. Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
    A memory grouping method for sharing memory BIST logic. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:671-676 [Conf]
  132. Daisuke Kosaka, Makoto Nagata
    Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:677-682 [Conf]
  133. Xiren Wang, Wenjian Yu, Zeyi Wang
    A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:683-688 [Conf]
  134. Zuochang Ye, Zhiping Yu
    Parasitics extraction involving 3-D conductors based on multi-layered Green's function. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:689-693 [Conf]
  135. Di Long, Xianlong Hong, Sheqin Dong
    Signal-path driven partition and placement for analog circuit. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:694-699 [Conf]
  136. Xiaoying Wang, Lars Hedrich
    An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:700-705 [Conf]
  137. Kenta Yamada, Noriaki Oda
    Statistical corner conditions of interconnect delay (corner LPE specifications). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:706-711 [Conf]
  138. Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy
    Speed binning aware design methodology to improve profit under parameter variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:712-717 [Conf]
  139. Vineet Agarwal, Janet Meiling Wang
    Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:718-723 [Conf]
  140. Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang
    A probabilistic analysis of pipelined global interconnect under process variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:724-729 [Conf]
  141. Fangyi Luo, Yongbo Jia, Wayne Wei-Ming Dai
    Yield-preferred via insertion based on novel geotopological technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:730-735 [Conf]
  142. Jian-Wen Chen, Chao-Yang Kao, Youn-Long Lin
    Introduction to H.264 advanced video coding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:736-741 [Conf]
  143. Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang
    Algorithms and DSP implementation of H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:742-749 [Conf]
  144. Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
    Hardware architecture design of an H.264/AVC video codec. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:750-757 [Conf]
  145. Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, Myung Hoon Sunwoo
    ASIP approach for implementation of H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:758-764 [Conf]
  146. Minsik Cho, Hongjoong Shin, David Z. Pan
    Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:765-770 [Conf]
  147. Yong Zhan, Yan Feng, Sachin S. Sapatnekar
    A fixed-die floorplanning algorithm using an analytical approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:771-776 [Conf]
  148. Chien-Chang Chen, Wai-Kei Mak
    A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:777-782 [Conf]
  149. Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai
    Design space exploration for minimizing multi-project wafer production cost. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:783-788 [Conf]
  150. Michael G. Wrighton, André DeHon
    SAT-based optimal hypergraph partitioning with replication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:789-795 [Conf]
  151. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
    Finding optimal L1 cache configuration for embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:796-801 [Conf]
  152. Hongwei Zhu, Ilie I. Luican, Florin Balasa
    Memory size computation for multimedia processing applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:802-807 [Conf]
  153. Mahmut T. Kandemir, Guangyu Chen, Feihui Li
    Maximizing data reuse for minimizing memory space requirements and execution cycles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:808-813 [Conf]
  154. Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu
    Compiler-Guided data compression for reducing memory consumption of embedded applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:814-819 [Conf]
  155. Javed Absar, Francky Catthoor
    Analysis of scratch-pad and data-cache performance using statistical methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:820-825 [Conf]
  156. Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
    Efficient early stage resonance estimation techniques for C4 package. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:826-831 [Conf]
  157. Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai
    Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:832-837 [Conf]
  158. Sarvesh H. Kulkarni, Dennis Sylvester
    Power distribution techniques for dual VDD circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:838-843 [Conf]
  159. Changhao Yan, Wenjian Yu, Zeyi Wang
    Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:844-849 [Conf]
  160. Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri
    Controlling inductive cross-talk and power in off-chip buses using CODECs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:850-855 [Conf]
  161. Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto
    A new test and characterization scheme for 10+ GHz low jitter wide band PLL. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:856-859 [Conf]
  162. Yukio Watanabe, Balazs Sallay, Brad Michael, Daniel Brokenshire, Gavin Meil, Hazim Shafi, Daisuke Hiraoka
    An SPU reference model for simulation, random test generation and verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:860-866 [Conf]
  163. Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong
    A cycle accurate power estimation tool. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:867-870 [Conf]
  164. Dac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel
    Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:871-878 [Conf]
  165. Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert P. Dick, Li Shang
    TAPHS: thermal-aware unified physical-level and high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:879-885 [Conf]
  166. Yu Pu, Yajun Ha
    An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:886-891 [Conf]
  167. Preeti Ranjan Panda
    Abridged addressing: a low power memory addressing strategy. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:892-897 [Conf]
  168. Roberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto
    Using speculative computation and parallelizing techniques to improve scheduling of control based designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:898-904 [Conf]
  169. Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi
    Worst case execution time analysis for synthesized hardware. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:905-910 [Conf]
  170. Ying Tan, Parth Malani, Qinru Qiu, Qing Wu
    Workload prediction and dynamic voltage scaling for MPEG decoding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:911-916 [Conf]
  171. Yen-Jen Chang
    Lazy BTB: reduce BTB energy consumption using dynamic profiling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:917-922 [Conf]
  172. Yuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy
    Cache size selection for performance, energy and reliability of time-constrained systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:923-928 [Conf]
  173. Priya Unnikrishnan, Mahmut T. Kandemir, Feihui Li
    Reducing dynamic compilation overhead by overlapping compilation and execution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:929-934 [Conf]
  174. Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya
    Functional modeling techniques for efficient SW code generation of video codec applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:935-940 [Conf]
  175. Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
    Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:941-946 [Conf]
  176. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    Parameterized block-based non-gaussian statistical gate timing analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:947-952 [Conf]
  177. Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
    Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:953-958 [Conf]
  178. Mongkol Ekpanyapong, Thaisiri Watewai, Sung Kyu Lim
    Statistical Bellman-Ford algorithm with an application to retiming. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:959-964 [Conf]
  179. Liang Deng, Martin D. F. Wong
    An exact algorithm for the statistical shortest path problem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:965-970 [Conf]
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