Conferences in DBLP
Satoru Ito Challenging device innovation. [Citation Graph (0, 0)][DBLP ] Conf ] Yukichi Niwa Effective platform-based development for large-scale systems design. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto L. Sangiovanni-Vincentelli Automotive electronics: steady growth for years to come! [Citation Graph (0, 0)][DBLP ] Conf ] Xingwen Xu , Shinji Kimura , Kazunari Horikawa , Takehiko Tsuchiya Transition-based coverage estimation for symbolic model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Bijan Alizadeh Word level functional coverage computation. [Citation Graph (0, 0)][DBLP ] Conf ] Prasenjit Basu , Sayantan Das , Pallab Dasgupta , Partha Pratim Chakrabarti Discovering the input assumptions in specification refinement coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Zaher S. Andraus , Mark H. Liffiton , Karem A. Sakallah Refinement strategies for verification methods based on datapath abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Jui (Song-Ra) Pan , Kwang-Ting Cheng , John Moondanos , Ziyad Hanna Generation of shorter sequences for high resolution error diagnosis using sequential SAT. [Citation Graph (0, 0)][DBLP ] Conf ] Sudeep Pasricha , Nikil D. Dutt , Mohamed Ben-Romdhane Constraint-driven bus matrix synthesis for MPSoC. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Wu , Bashir M. Al-Hashimi , Marcus T. Schmitz Improving routing efficiency for network-on-chip through contention-aware input selection. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Guo , Antonis Papanikolaou , Pol Marchal , Francky Catthoor Physical design implementation of segmented buses to reduce communication energy. [Citation Graph (0, 0)][DBLP ] Conf ] Mário P. Véstias , Horácio C. Neto Co-synthesis of a configurable SoC platform based on a network on chip architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad Omer Cheema , Omar Hammami Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Ramalingam , Sreekumar V. Kodakara , Anirudh Devgan , David Z. Pan Robust analytical gate delay modeling for low voltage circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shahin Nazarian , Massoud Pedram , Tao Lin , Emre Tuncer CGTA: current gain-based timing analysis for logic cells. [Citation Graph (0, 0)][DBLP ] Conf ] Shuo Zhou , Bo Yao , Hongyu Chen , Yi Zhu , Chung-Kuan Cheng , Michael Hutton Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. [Citation Graph (0, 0)][DBLP ] Conf ] Sachin Shrivastava , Rajendra Pratap , Harindranath Parameswaran , Manuj Verma Crosstalk analysis using reconvergence correlation. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown Process-induced skew reduction in nominal zero-skew clock trees. [Citation Graph (0, 0)][DBLP ] Conf ] Tadayoshi Enomoto , Nobuaki Kobayashi A low dynamic power and low leakage power 90-nm CMOS square-root circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Lili Zhou , Cherry Wakayama , Nuttorn Jangkrajarng , Bo Hu , C.-J. Richard Shi A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Senger , Eric D. Marsman , Michael S. McCorquodale , Richard B. Brown A 16-bit, low-power microsystem with monolithic MEMS-LC clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Ying Tsui , Hui Shao , Wing-Hung Ki , Feng Su Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. [Citation Graph (0, 0)][DBLP ] Conf ] Koichi Ishida , Atit Tamtrakarn , Takayasu Sakurai A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. [Citation Graph (0, 0)][DBLP ] Conf ] Fangqing Chu , Wei Li , Junyan Ren An implementation of a CMOS down-conversion mixer for GSM1900 receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Yat-Hei Lam , Suet-Chui Koon , Wing-Hung Ki , Chi-Ying Tsui Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Yat-Hei Lam , Wing-Hung Ki , Chi-Ying Tsui Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuya Fukazawa , Koichiro Noguchi , Makoto Nagata , Kazuo Taki A built-in power supply noise probe for digital LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Minoru Watanabe , Fuminori Kobayashi A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuya Katsuki , Manabu Kotani , Kazutoshi Kobayashi , Hidetoshi Onodera Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. [Citation Graph (0, 0)][DBLP ] Conf ] Tatsuyuki Ishikawa , Kazunori Shimizu , Takeshi Ikenaga , Satoshi Goto High-throughput decoder for low-density parity-check code. [Citation Graph (0, 0)][DBLP ] Conf ] Nursani Rahmatullah , Arif E. Nugroho Hardware implementation of super minimum all digital FM demodulator. [Citation Graph (0, 0)][DBLP ] Conf ] Bita Gorjiara , Mehrdad Reshadi , Daniel D. Gajski Designing a custom architecture for DCT using NISC technology. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Hao Ou , Tay-Jyi Lin , Chao-Wei Huang , Yu-Ting Kuo , Chie-Min Chao , Chih-Wei Liu , Chein-Wei Jen A 52mW 1200MIPS compact DSP for multi-core media SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Suh Ho Lee , Ji Hwan Park , Seon Wook Kim , Sung Jea Ko , Suki Kim Implementation of H.264/AVC decoder for mobile video applications. [Citation Graph (0, 0)][DBLP ] Conf ] Min Wu , Xiaoyang Zeng , Jun Han , Yongyi Wu , Yibo Fan A high-performance platform-based SoC for information security. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Nishimura , Takuji Miki , Hiroaki Sugiura , Yuki Matsumoto , Masatsugu Kobayashi , Toshiyuki Kato , Tsutomu Eda , Hironori Yamauchi Configurable multi-processor architecture and its processor element design. [Citation Graph (0, 0)][DBLP ] Conf ] Hansu Cho , Samar Abdi , Daniel Gajski Design and implementation of transducer for ARM-TMS communication. [Citation Graph (0, 0)][DBLP ] Conf ] Seung Woo Son , Guangyu Chen , Mahmut T. Kandemir , Feihui Li Energy savings through embedded processing on disk system. [Citation Graph (0, 0)][DBLP ] Conf ] Guilin Chen , Mahmut T. Kandemir , Feihui Li Energy-aware computation duplication for improving reliability in embedded chip multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Guilin Chen , Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin Object duplication for improving reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli Mapping and configuration methods for multi-use-case networks on chips. [Citation Graph (0, 0)][DBLP ] Conf ] Hyeyoung Hwang , Taewook Oh , Hyunuk Jung , Soonhoi Ha Conversion of reference C code to dataflow model: H.264 encoder case study. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Li , Yiran Chen , Kaushik Roy , Cheng-Kok Koh SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. [Citation Graph (0, 0)][DBLP ] Conf ] Robert D. Mullins , Andrew West , Simon W. Moore The design and implementation of a low-latency on-chip network. [Citation Graph (0, 0)][DBLP ] Conf ] Shen-Yu Shih , Cheng-Ru Chang , Youn-Long Lin A near optimal deblocking filter for H.264 advanced video coding. [Citation Graph (0, 0)][DBLP ] Conf ] K. Yamaoka , Takashi Morimoto , Hidekazu Adachi , Tetsushi Koide , Hans Jürgen Mattausch Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. [Citation Graph (0, 0)][DBLP ] Conf ] Ismail Kadayif , Mahmut T. Kandemir , Feihui Li Prefetching-aware cache line turnoff for saving leakage energy. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Min Xie A robust detailed placement for mixed-size IC designs. [Citation Graph (0, 0)][DBLP ] Conf ] Natarajan Viswanathan , Min Pan , Chris C. N. Chu FastPlace 2.0: an efficient analytical placer for mixed-mode designs. [Citation Graph (0, 0)][DBLP ] Conf ] Chanseok Hwang , Massoud Pedram Timing-driven placement based on monotone cell ordering constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jinjun Xiong , Yiu-Chung Wong , Egino Sarto , Lei He Constraint driven I/O planning and placement for chip-package co-design. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Yang Peng , Wen-Chang Chao , Yao-Wen Chang , Jyh-Herng Wang Simultaneous block and I/O buffer floorplanning for flip-chip design. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Zhan , Brent Goplen , Sachin S. Sapatnekar Electrothermal analysis and optimization techniques for nanoscale integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kaustav Banerjee , Sheng-Chih Lin , Navin Srivastava Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ja Chun Ku , Yehea I. Ismail Area optimization for leakage reduction and thermal stability in nanometer scale technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Aditya Bansal , Mesut Meterelliyoz , Siddharth Singh , Jung Hwan Choi , Jayathi Murthy , Kaushik Roy Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Kettle , Andy King An anytime symmetry detection algorithm for ROBDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Hong Su , Chun-Yao Wang High level equivalence symmetric input identification. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Hsu Huang , Chia-Ming Chang , Yow-Tyng Nieh Fast multi-domain clock skew scheduling for peak current reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Bakhtiar Affendi Rosdi , Atsushi Takahashi Low area pipelined circuits by multi-clock cycle paths and clock scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Yamashita , Katsunori Tanaka , Hideyuki Takada , Koji Obata , Kazuyoshi Takagi A transduction-based framework to synthesize RSFQ circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaolue Lai , Jaijeet S. Roychowdhury Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomena. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. McCorquodale , James L. McCann , Richard B. Brown Newton : a library-based analytical synthesis tool for RF-MEMS resonators.Citation Graph (0, 0)][DBLP ] Conf ] Qingqi Dou , Jacob A. Abraham Jitter decomposition in ring oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Goyal , Xiaolue Lai , Jaijeet S. Roychowdhury A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels. [Citation Graph (0, 0)][DBLP ] Conf ] S. H. Rasouli , A. Amirabadi , A. Seyedi , Ali Afzali-Kusha Double edge triggered Feedback Flip-Flop in sub 100NM technology. [Citation Graph (0, 0)][DBLP ] Conf ] Kuang-Yao Lee , Ting-Chi Wang Post-routing redundant via insertion for yield/reliability improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Tianpei Zhang , Yong Zhan , Sachin S. Sapatnekar Temperature-aware routing in 3D ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Vogel , Martin D. F. Wong Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Li , Weiping Shi An O (mn ) time algorithm for optimal buffer insertion of nets with m sinks. [Citation Graph (0, 0)][DBLP ] Conf ] Man Chung Hon Spec-based flip-flop and latch repeater planning. [Citation Graph (0, 0)][DBLP ] Conf ] Sang Lyul Min , Eyee Hyun Nam Current trends in flash memory technology: invited paper. [Citation Graph (0, 0)][DBLP ] Conf ] Tei-Wei Kuo , Jen-Wei Hsieh , Li-Pin Chang , Yuan-Hao Chang Configurability of performance and overheads in flash management. [Citation Graph (0, 0)][DBLP ] Conf ] Noriyuki Ito , Akira Kanuma , Daisuke Maruyama , Hitoshi Yamanaka , Tsuyoshi Mochizuki , Osamu Sugawara , Chihiro Endoh , Masahiro Yanagida , Takeshi Kono , Yutaka Isoda , Kazunobu Adachi , Takahisa Hiraide , Shigeru Nagasawa , Yaroku Sugiyama , Eizo Ninoi Delay defect screening for a 2.16GHz SPARC64 microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Masayasu Fukunaga , Seiji Kajihara , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato A dynamic test compaction procedure for high-quality path delay testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Chiang Wu , Cheng-Tao Hsieh , Shih-Chieh Chang Delay variation tolerance for domino circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Yang , Kwang-Ting Cheng Efficient identification of multi-cycle false path. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine Shu-Min Li , Yao-Wen Chang , Chauchin Su , Chung-Len Lee , Jwu E. Chen IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. [Citation Graph (0, 0)][DBLP ] Conf ] Marius Bonaciu , Aimen Bouchhima , Mohamed-Wassim Youssef , Xi Chen , Wander O. Cesário , Ahmed Amine Jerraya High-level architecture exploration for MPEG4 encoder with custom parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Shinobu Nagayama , Tsutomu Sasao , Jon T. Butler Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Ashok Jagannathan , Yuchun Ma , Glenn Reinman , Jie Wei , Yan Zhang An automated design flow for 3D microarchitecture evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Feng Wang 0004 , Mahmut T. Kandemir , Yuan Xie Optimal topology exploration for application-specific 3D architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jesús Tabero , Julio Septién , Hortensia Mecha , Daniel Mozos Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Zhao Li , C.-J. Richard Shi A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyotaka Yamamura , Wataru Kuroki An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Baohua Wang , Pinaki Mazumder Optimization of circuit trajectories: an auxiliary network approach. [Citation Graph (0, 0)][DBLP ] Conf ] Jitesh Jain , Stephen Cauley , Cheng-Kok Koh , Venkataramanan Balakrishnan SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. [Citation Graph (0, 0)][DBLP ] Conf ] Zhengyong Zhu , Rui Shi , Chung-Kuan Cheng , Ernest S. Kuh An unconditional stable general operator splitting method for transistor level transient analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Michaela Guiney , Eric Leavitt An introduction to OpenAccess: an open source data model and API for IC design. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshio Inoue Open access overview "industrial experience". [Citation Graph (0, 0)][DBLP ] Conf ] Hillel Ofek EDA vendor adoption. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Papa , Igor L. Markov , Philip Chong Utility of the OpenAccess database in academic research. [Citation Graph (0, 0)][DBLP ] Conf ] Ilya Wagner , Valeria Bertacco , Todd M. Austin Depth-driven verification of simultaneous interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Man-Yun Su , Che-Hua Shih , Juinn-Dar Huang , Jing-Yang Jou FSM-based transaction-level functional coverage for interface compliance verification. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuyuki Ohba , Kohji Takano Hardware debugging method based on signal transitions and transactions. [Citation Graph (0, 0)][DBLP ] Conf ] Junghee Lee , Joonhwan Yi Cycle error correction in asynchronous clock modeling for cycle-based simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroki Nakahara , Tsutomu Sasao , Munehiro Matsuura A fast logic simulator using a look up table cascade emulator. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Rong , Massoud Pedram Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system. [Citation Graph (0, 0)][DBLP ] Conf ] Ernesto Wandeler , Lothar Thiele Optimal TDMA time slot and cycle length allocation for hard real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hector Posadas , Jesús Ádamez , Pablo Sánchez , Eugenio Villar , Francisco Blasco POSIX modeling in SystemC. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil Dutt PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunok Oh , Nikil Dutt , Soonhoi Ha Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Sean X. Shi , David Z. Pan Wire sizing with scattering effect for nanoscale interconnection. [Citation Graph (0, 0)][DBLP ] Conf ] Ya-Chi Yang , Cheng-Kok Koh , Venkataramanan Balakrishnan Adaptive admittance-based conductor meshing for interconnect analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Tsuchiya , Masanori Hashimoto , Hidetoshi Onodera Interconnect RL extraction at a single representative frequency. [Citation Graph (0, 0)][DBLP ] Conf ] Mengsheng Zhang , Wenjian Yu , Yu Du , Zeyi Wang An efficient algorithm for 3-D reluctance extraction considering high frequency effect. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaolue Lai , Jaijeet S. Roychowdhury Macromodelling oscillators using Krylov-subspace methods. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Kitahara , Hiroyuki Hara , Shinichiro Shiratake , Yoshiki Tsukiboshi , Tomoyuki Yoda , Tetsuaki Utsumi , Fumihiro Minami Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Imai , Atsuki Inoue , Motoaki Matsumura , Kenichi Kawasaki , Atsuhiro Suga Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. [Citation Graph (0, 0)][DBLP ] Conf ] Masafumi Onouchi , Tetsuya Yamada , Kimihiro Morikawa , Isamu Mochizuki , Hidetoshi Sekine A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation. [Citation Graph (0, 0)][DBLP ] Conf ] Ikhwan Lee , Hyunsuk Kim , Peng Yang , Sungjoo Yoo , Eui-Young Chung , Kyu-Myung Choi , Jeong-Taek Kong , Soo-Kwan Eo PowerVi P: Soc power estimation framework at transaction level. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay V. Kumar , Chris H. Kim , Sachin S. Sapatnekar Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hyung-Ock Kim , Youngsoo Shin Analysis and optimization of gate leakage current of power gating circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Naoaki Ohkubo , Kimiyoshi Usami Delay modeling and static timing analysis for MTCMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Hui Huang , Po-Yuan Chen , TingTing Hwang Switching-activity driven gate sizing and Vth assignment for low power design. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Liu , Yici Cai , Qiang Zhou , Xianlong Hong Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. [Citation Graph (0, 0)][DBLP ] Conf ] Sanggyu Park , Sang-yong Yoon , Soo-Ik Chae Reusable component IP design using refinement-based design environment. [Citation Graph (0, 0)][DBLP ] Conf ] Shunitsu Kohara , Naoki Tomono , Jumpei Uchida , Yuichiro Miyaoka , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Hua Chen , Geeng-Wei Lee , Juinn-Dar Huang , Jing-Yang Jou A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. [Citation Graph (0, 0)][DBLP ] Conf ] Qubo Hu , Arnout Vandecappelle , Martin Palkovic , Per Gunnar Kjeldsberg , Erik Brockmeyer , Francky Catthoor Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications. [Citation Graph (0, 0)][DBLP ] Conf ] Andhi Janapsatya , Aleksandar Ignjatovic , Sri Parameswaran A novel instruction scratchpad memory optimization method based on concomitance metric. [Citation Graph (0, 0)][DBLP ] Conf ] Zhen Cao , Tong Jing , Yu Hu , Yiyu Shi , Xianlong Hong , Xiaodong Hu , Guiying Yan DraXRouter: global routing in X-Architecture with dynamic resource assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Noriyuki Ito , Hideaki Katagiri , Ryoichi Yamashita , Hiroshi Ikeda , Hiroyuki Sugiyama , Hiroaki Komatsu , Yoshiyasu Tanamura , Akihiko Yoshitake , Kazuhiro Nonomura , Kinya Ishizaka , Hiroaki Adachi , Yutaka Mori , Yutaka Isoda , Yaroku Sugiyama Diagonal routing in high performance microprocessor design. [Citation Graph (0, 0)][DBLP ] Conf ] Yiyu Shi , Tong Jing , Lei He , Zhe Feng 0002 , Xianlong Hong CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. [Citation Graph (0, 0)][DBLP ] Conf ] Tai-Chen Chen , Yao-Wen Chang , Shyh-Chang Lin A novel framework for multilevel full-chip gridless routing. [Citation Graph (0, 0)][DBLP ] Conf ] Yoichi Tomioka , Atsushi Takahashi Monotonic parallel and orthogonal routing for single-layer ball grid array packages. [Citation Graph (0, 0)][DBLP ] Conf ] X.-L. Huang , J.-L. Huang A routability constrained scan chain ordering technique for test power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Youhua Shi , Nozomu Togawa , Shinji Kimura , Masao Yanagisawa , Tatsuo Ohtsuki FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Kewal K. Saluja , Hiroshi Takahashi , Shin-ya Kobayashi , Yuzo Takamatsu Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Goel , Swarup Bhunia , Hamid Mahmoodi-Meimand , Kaushik Roy Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. [Citation Graph (0, 0)][DBLP ] Conf ] Masahide Miyazaki , Tomokazu Yoneda , Hideo Fujiwara A memory grouping method for sharing memory BIST logic. [Citation Graph (0, 0)][DBLP ] Conf ] Daisuke Kosaka , Makoto Nagata Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation. [Citation Graph (0, 0)][DBLP ] Conf ] Xiren Wang , Wenjian Yu , Zeyi Wang A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles. [Citation Graph (0, 0)][DBLP ] Conf ] Zuochang Ye , Zhiping Yu Parasitics extraction involving 3-D conductors based on multi-layered Green's function. [Citation Graph (0, 0)][DBLP ] Conf ] Di Long , Xianlong Hong , Sheqin Dong Signal-path driven partition and placement for analog circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoying Wang , Lars Hedrich An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Kenta Yamada , Noriaki Oda Statistical corner conditions of interconnect delay (corner LPE specifications). [Citation Graph (0, 0)][DBLP ] Conf ] Animesh Datta , Swarup Bhunia , Jung Hwan Choi , Saibal Mukhopadhyay , Kaushik Roy Speed binning aware design methodology to improve profit under parameter variations. [Citation Graph (0, 0)][DBLP ] Conf ] Vineet Agarwal , Janet Meiling Wang Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA). [Citation Graph (0, 0)][DBLP ] Conf ] Navneeth Kankani , Vineet Agarwal , Janet Meiling Wang A probabilistic analysis of pipelined global interconnect under process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Fangyi Luo , Yongbo Jia , Wayne Wei-Ming Dai Yield-preferred via insertion based on novel geotopological technology. [Citation Graph (0, 0)][DBLP ] Conf ] Jian-Wen Chen , Chao-Yang Kao , Youn-Long Lin Introduction to H.264 advanced video coding. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-Chih Lin , Yu-Jen Wang , Kai-Ting Cheng , Shang-Yu Yeh , Wei-Nien Chen , Chia-Yang Tsai , Tian-Sheuan Chang , Hsueh-Ming Hang Algorithms and DSP implementation of H.264/AVC. [Citation Graph (0, 0)][DBLP ] Conf ] Tung-Chien Chen , Chung-Jr Lian , Liang-Gee Chen Hardware architecture design of an H.264/AVC video codec. [Citation Graph (0, 0)][DBLP ] Conf ] Sung Dae Kim , Jeong Hoo Lee , Chung Jin Hyun , Myung Hoon Sunwoo ASIP approach for implementation of H.264/AVC. [Citation Graph (0, 0)][DBLP ] Conf ] Minsik Cho , Hongjoong Shin , David Z. Pan Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Zhan , Yan Feng , Sachin S. Sapatnekar A fixed-die floorplanning algorithm using an analytical approach. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Chang Chen , Wai-Kei Mak A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. [Citation Graph (0, 0)][DBLP ] Conf ] Rung-Bin Lin , Meng-Chiou Wu , Wei-Chiu Tseng , Ming-Hsine Kuo , Tsai-Ying Lin , Shr-Cheng Tsai Design space exploration for minimizing multi-project wafer production cost. [Citation Graph (0, 0)][DBLP ] Conf ] Michael G. Wrighton , André DeHon SAT-based optimal hypergraph partitioning with replication. [Citation Graph (0, 0)][DBLP ] Conf ] Andhi Janapsatya , Aleksandar Ignjatovic , Sri Parameswaran Finding optimal L1 cache configuration for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hongwei Zhu , Ilie I. Luican , Florin Balasa Memory size computation for multimedia processing applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Guangyu Chen , Feihui Li Maximizing data reuse for minimizing memory space requirements and execution cycles. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Guangyu Chen , Mahmut T. Kandemir , Ibrahim Kolcu Compiler-Guided data compression for reducing memory consumption of embedded applications. [Citation Graph (0, 0)][DBLP ] Conf ] Javed Absar , Francky Catthoor Analysis of scratch-pad and data-cache performance using statistical methods. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Shi , Yici Cai , Sheldon X.-D. Tan , Xianlong Hong Efficient early stage resonance estimation techniques for C4 package. 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