Conferences in DBLP
Michael C.-J. Lin , Youn-L. Lin A VLSI implementation of the blowfish encryption/decryption algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Yuk-Hang Leung , Chi-Ying Tsui , Roger S. Cheng VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Ying Tsui , Louis Chung-Yin Kwan , Chin-Tau Lea VLSI implementation of a switch fabric for mixed ATM and IP traffic. [Citation Graph (0, 0)][DBLP ] Conf ] J.-K. Lee , Seung-Min Lee , Mike Myung-Ok Lee , D.-W. Lee , Y.-C. Kim , S.-J. Jeong Design of digital neural cell scheduler for intelligent IB-ATM switch. [Citation Graph (0, 0)][DBLP ] Conf ] Shin'ichi Wakabayashi , Tetsushi Koide , Nayoshi Toshine , Masataka Yamane , Hajime Ueno Genetic algorithm accelerator GAA-II. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Tsun Huang , Jing-Reng Huang , Cheng-Wen Wu A programmable built-in self-test core for embedded memories. [Citation Graph (0, 0)][DBLP ] Conf ] Fan Mo , Yihua Zhang , Jun Yu , Qianling Zhang An algorithm for VLSI implementation of highly efficient cubic-polynomial evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Tin-Y. Tang , Chin-S. Choy , Pui-L. Siu , Cheong-F. Chan Design of self-timed asynchronous Booth's multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Seung-Min Lee , Jin-Hong Chung , Hying-S. Yoon , Mike Myung-Ok Lee High speed and ultra-low power 16×16 MAC deisgn using TG techniques for web-based multimedia system. [Citation Graph (0, 0)][DBLP ] Conf ] Noriaki Takeda , Mitsuru Homma , Makoto Nagata , Takashi Morie , Atsushi Iwata A smart imager for the vision processing front-END. [Citation Graph (0, 0)][DBLP ] Conf ] Tomohiro Nezuka , Takafumi Fujita , Makoto Ikeda , Kunihiro Asada A binary image sensor with flexible motion vector detection using block matching method. [Citation Graph (0, 0)][DBLP ] Conf ] Kenichi Murakoshi , Takashi Morie , Makoto Nagata , Atsushi Iwata An arbitrary chaos generator core curcuit using PWM/PPM signals. [Citation Graph (0, 0)][DBLP ] Conf ] Shinji Kimura , Hiroyuki Kida , Kazuyoshi Takagi , Tatsumori Abematsu , Katsumasa Watanabe An application specific Java processor with reconfigurabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Sasaki , Hitoshi Maruyama , Hideaki Tsukioka , Nobuyoshi Shoji , Hiroaki Kobayashi , Tadao Nakamura Reconfigurable synchronized dataflow processor. [Citation Graph (0, 0)][DBLP ] Conf ] Naoki Nishimura , Takahiro Sasaki , Tetsuo Hironaka Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Kawaguchi , Takayuki Suzuki , Hideharu Amano A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system. [Citation Graph (0, 0)][DBLP ] Conf ] Hirofumi Sakamoto , Ken'ichiro Uda , Bu-Y. Lee , Hiroyuki Ochi , Kazuo Taki , Takao Tsuda A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. [Citation Graph (0, 0)][DBLP ] Conf ] Joonho Lim , Dong-G. Kim , Sang-C. Kang , Soo-Ik Chae An 8×8 nRERL serial multiplier for ultra-low-power aplications. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Gajski , Allen C.-H. Wu , Viraphol Chaiyakul , Shojiro Mori , Tom Nukiyama , Pierre Bricaud Embedded tutorial: essential issues for IP reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Nong Fan , Viraphol Chaiyakul , Daniel Gajski Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Dömer , Daniel Gajski Reuse and protection of intellectual property in the SpecC system. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Qu , Jennifer L. Wong , Miodrag Potkonjak Fair watermarking techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Riccardo Forth , Paul Molitor An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Jawahar Jain , Koichiro Takayama , Masahiro Fujita Automatic partitioning for efficient combinatorial verification. [Citation Graph (0, 0)][DBLP ] Conf ] Yukihiro Iguchi , Tsutomu Sasao , Munehiro Matsuura , Atsumu Iseno A hardware simulation engine based on decision diagrams (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] Subir K. Roy , Hiroaki Iwashita , Tsuneo Nakata Formal verification based on assume and guarantee approach - a case study (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] Kazuhiro Nakamura , Shinji Maruoka , Shinji Kimura , Katsumasa Watanabe Multi-clock path analysis using propositional satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Yukiko Kubo , Yasuhiro Takashima , Shigetoshi Nakatake , Yoji Kajitani Self-reforming routing for stochastic search in VLSI interconnection layout. [Citation Graph (0, 0)][DBLP ] Conf ] Naofumi Tsujii , Katsutoshi Baba , Shuji Tsukiyama An interconnect topology optimization by a tree transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Deguchi , Tetsushi Koide , Shin'ichi Wakabayashi Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. [Citation Graph (0, 0)][DBLP ] Conf ] Zhang Yan , Wang Baohua , Yici Cai , Xianlong Hong Area routing oriented hierarchical corner stitching with partial bin. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen S. Brown , Jeet Asher , William H. Mangione-Smith Offline program re-mapping to improve branch prediction efficiency in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh Ramanathan , Ravindra Jejurikar , Rajesh K. Gupta Timing driven co-design of networked embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kimiyoshi Usami , Mutsunori Igarashi Low-power design methodology and applications utilizing dual supply voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Xie , Wayne Wolf Co-synthesis with custom ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Heng-Liang Huang , Jiing-Yuan Lin , Wen-Zen Shen , Jing-Yang Jou A new method for constructing IP level power model based on power sensitivity. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Givargis , Frank Vahid , Jörg Henkel A hybrid approach for core-based system-level power modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Allan Rae , Sri Parameswaran Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Sundararajan , Keshab K. Parhi Synthesis of low power folded programmable coefficient FIR digital filters (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Songjie Xu Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Michael Herz , Thomas Hoffmann , Ulrich Nageldinger KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. [Citation Graph (0, 0)][DBLP ] Conf ] Byungil Jeong , Sungjoo Yoo , Sunghyun Lee , Kiyoung Choi Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Toshihiko Takahashi A new encoding scheme for rectangle packing problem. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew A. Kennings , Igor L. Markov Analytical minimization of half-perimeter wirelength. [Citation Graph (0, 0)][DBLP ] Conf ] Maogang Wang , Majid Sarrafzadeh Modeling and minimization of routing congestion. [Citation Graph (0, 0)][DBLP ] Conf ] King L. Tai System-in-package (SIP): challenges and opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Albert Lin Taiwan foundry for system-in-package (SIP). [Citation Graph (0, 0)][DBLP ] Conf ] Michael X. Wang , Katsuharu Suzuki , Wayne Wei-Ming Dai , Yee L. Low , Kevin J. O'Conner , King L. Tai Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology. [Citation Graph (0, 0)][DBLP ] Conf ] Minqing Liu , Wayne Wei-Ming Dai Modeling and analysis of integrated spiral inductors for RF system-in-package. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Kiyoung Choi Narrow bus encoding for low power systems. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Sundararajan , Keshab K. Parhi Data transmission over a bus with peak-limited transition activity. [Citation Graph (0, 0)][DBLP ] Conf ] Jinn-Shyan Wang , Po-Hui Yang Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Ing-Jer Huang , Dao-Zhen Chen A new approach to assembly software retargeting for microcontrollers. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Leupers Register allocation for common subexpressions in DSP data paths. [Citation Graph (0, 0)][DBLP ] Conf ] Johnson S. Kin , Chunho Lee , William H. Mangione-Smith , Miodrag Potkonjak A technique for QoS-based system partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Debatosh Debnath , Tsutomu Sasao Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Yamashita , Hiroshi Sawada , Akira Nagoya An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao , Ken-ichi Kurimoto Three parameters to find functional decompositions. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Kikuchi , Tetsuo Sasaki , Tohru Hashimoto , Kazuhisa Miyamoto Delay-optimal wiring plan for the microprocessor of high performance computing machines. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Yu , Xianlong Hong , Yici Cai MMP: a novel placement algorithm for combined macro block and standard cell layout design. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Tianming Kong , Faming Liang , Jun S. Liu , Wing Hung Wong , Dongmin Xu Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. [Citation Graph (0, 0)][DBLP ] Conf ] Xiang-Dong Tan , C.-J. Richard Shi Symbolic circuit-noise analysis and modeling with determinant decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiyuki Kawakami , Jingkun Fang , Hirokazu Yonezawa , Nobufusa Iwanishi , Lifeng Wu , Alvin I-Hsien Chen , Norio Koike , Ping Chen , Chune-Sin Yeh , Zhihong Liu Gate-level aged timing simulation methodology for hot-carrier reliability assurance. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuneo Terasawa Embedded tutorial: subwavelength lithography. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh V. Gupta Embedded tutorial: IC design technology for building system-on-a-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Mizuki Takahashi , Nagisa Ishiura , Akihisa Yamada , Takashi Kambe Thread partitioning method for hardware compiler bach. [Citation Graph (0, 0)][DBLP ] Conf ] Nozomu Togawa , Masayuki Ienaga , Masao Yanagisawa , Tatsuo Ohtsuki An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] Taewhan Kim , Junhyung Um A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] Norbert Imlig , Ryusuke Konishi , Tsunemichi Shiozawa , Kiyoshi Oguri , Kouichi Nagami , Hideyuki Ito , Minoru Inamori , Hiroshi Nakada Communicating logic: an alternative embedded stream processing paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuhito Ito A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Masakazu Yamashina , Masato Motomura Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. [Citation Graph (0, 0)][DBLP ] Conf ] Chunhong Chen , Majid Sarrafzadeh Power reduction by simultaneous voltage scaling and gate sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Massoud Pedram , Xunwei Wu Analysis of power-clocked CMOS with application to the design of energy-recovery circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Xunwei Wu , Jian Wei , Massoud Pedram , Qing Wu Low-power design of sequential circuits using a quasi-synchronous derived clock. [Citation Graph (0, 0)][DBLP ] Conf ] José C. Monteiro , Arlindo L. Oliveira FSM decomposition by direct circuit manipulation applied to low power design. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano , Olivier Coudert , Patrick Groeneveld , Leon Stok , Ralph H. J. M. Otten Timing closure: the solution and its problems. [Citation Graph (0, 0)][DBLP ] Conf ] M. Tanaka , N. Tokida , T. Okagaki , Michiko Miura-Mattausch , Walter Hansch , Hans Jürgen Mattausch High performance of short-channel MOSFETs due to an elevated central-channel doping. [Citation Graph (0, 0)][DBLP ] Conf ] Mikako Miyama , Shiro Kamohara Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej J. Strojwas Design for manufacturability: a path from system level to high yielding chips: embedded tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey Low-power silicon architecture for wireless communications: embedded tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Seongsoo Lee , Takayasu Sakurai Run-time power control scheme using software feedback loop for low-power real-time application. [Citation Graph (0, 0)][DBLP ] Conf ] Qing Wu , Qinru Qiu , Massoud Pedram An interleaved dual-battery power supply for battery-operated electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Ernst , Ahmed Amine Jerraya embedded system design with multiple languages: embedded tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Inki Hong , Darko Kirovski , Miodrag Potkonjak , Marios C. Papaefthymiou Symbolic debugging of globally optimized behavioral specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Sang-Joon Nam , Jun-Hee Lee , Byoung-Woon Kim , Yeon-Ho Im , Young-Su Kwon , Kyong-Gu Kang , Chong-Min Kyung Fast development of source-level debugging system using hardware emulation (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] Luc Séméria , Abhijit Ghosh Methodology for hardware/software co-verification in C/C++ (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] Tzu-Chieh Tien , Youn-Long Lin Performance-optimal clustering with retiming for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wangning Long , Yu-Liang Wu , Jinian Bian IBAW: an implication-tree based alternative-wiring logic transformation algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ramamurti Chandramouli , Vamsi K. Srikantam On mixture density and maximum likelihood power estimation via expectation-maximization. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Sung Kyu Lim Edge separability based circuit clustering with application to circuit partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Hsun-Cheng Lee , Ting-Chi Wang Feasible two-way circuit partitioning with complex resource constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Sung Kyu Lim Performance driven multiway partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jiangchun Gu , Zeyi Wang , Xianlong Hong Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. [Citation Graph (0, 0)][DBLP ] Conf ] Shuzhou Fang , Xiaobo Tang , Zeyi Wang , Xianlong Hong A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. [Citation Graph (0, 0)][DBLP ] Conf ] W. K. Kal , S. Y. Kim An analytic calculation method for delay time of RC-class interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Yang , Walter H. Ku , Chung-Kuan Cheng A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Koichi Nose , Takayasu Sakurai Optimization of VDD and VTH for low-power and high speed applications. [Citation Graph (0, 0)][DBLP ] Conf ] Nguyen Minh Duc , Takayasu Sakurai Compact yet high performance (CyHP) library for short time-to-market with new technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan-Bao Hsu , Kao-Shing Hwang , Chien-Yuan Pao , Jinn-Shyan Wang A new CMAC neural network architecture and its ASIC realization. [Citation Graph (0, 0)][DBLP ] Conf ] Naji Ghazal , A. Richard Newton , Jan M. Rabaey Retargetable estimation scheme for DSP architecture selection. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunok Oh , Soonhoi Ha Data memory minimization by sharing large size buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Kai Chang , Youn-Long Lin Array allocation taking into account SDRAM characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Nina Saxena , Jacob A. Abraham , Avijit Saha Causality based generation of directed test cases. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Yuzo Takamatsu , Kewal K. Saluja , Kozo Kinoshita Fault models and test generation for IDDQ testing: embedded tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Aikyo Issues on SOC testing in DSM area: embedded tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuhisa Okada , Takayuki Yamanouchi , Takashi Kambe A cell synthesis method for salicide process. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Chen , Andrew B. Kahng , Gabriel Robins , Alexander Zelikovsky Monte-Carlo algorithms for layout density control. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Furuie , Bao-Yu Song , Yukihiro Yoshida , Takao Onoye , Isao Shirakawa Layout generation of array cell for NMOS 4-phase dynamic logic (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] C. Lin , D. M. W. Leenaerts A new efficient method for substrate-aware device-level placement (short paper). [Citation Graph (0, 0)][DBLP ] Conf ] Mark M. Gourary , Sergey G. Rusakov , Sergey L. Ulyanov , Michael M. Zharov , Kiran K. Gullapalli , Brian J. Mulvaney The enchancing of efficiency of the harmonic balance analysis by adaptation of preconditioner to circuit nonlinearity. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Pi , C.-J. Richard Shi Analog-testability analysis by determinant-decision-diagrams based symbolic analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Tomohiro Fujita , Ken-ichi Okada , Hiroaki Fujita , Hidetoshi Onodera , Keikichi Tamaru A method for linking process-level variability to system performances. [Citation Graph (0, 0)][DBLP ] Conf ] Takayasu Sakurai Design challenges for 0.1um and beyond: embedded tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Su Kwon , In-Cheol Park , Chong-Min Kyung A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Hua Hong , Cheng-Wen Wu Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem. [Citation Graph (0, 0)][DBLP ] Conf ] Steven E. Schultz An introduction to SLDL and Rosetta. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Arnout SystemC standard. [Citation Graph (0, 0)][DBLP ] Conf ] Tommy Kuhn , Wolfgang Rosenstiel Java based object oriented hardware specification and synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Flake , Simon J. Davidmann Superlog, a unified design language for system-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Jia Liou , Angela Krstic , Kwang-Ting Cheng , Deb Aditya Mukherjee , Sandip Kundu Performance sensitivity analysis using statistical method and its applications to delay. [Citation Graph (0, 0)][DBLP ] Conf ] Huan-Chih Tsai , Kwang-Ting Cheng , Vishwani D. Agrawal A testability metric for path delay faults and its application. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Ohtake , Hiroki Wada , Toshimitsu Masuzawa , Hideo Fujiwara A non-scan DFT method at register-transfer level to achieve complete fault efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Jiun-Lang Huang , Kwang-Ting Cheng A sigma-delta modulation based BIST scheme for mixed-signal circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Deuk Jeon , Byeong-Lyeol Jean , Seung-Chul Lee , Sang-Min Yoo , Seung-Hoon Lee A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter. [Citation Graph (0, 0)][DBLP ] Conf ] Edoardo Charbon , Luis Miguel Silveira , Paolo Miliozzi A benchmark suite for substrate analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Nagata , Atsushi Iwata Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Haruyuki Tago , Kazuhiro Hashimoto , Nobuyuki Ikumi , Masato Nagamatsu , Masakazu Suzuoki , Yasuyuki Yamamoto Importance of CAD tools and methodology in high speed CPU design: invited talk. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Kamei , Hideaki Takeda , Yukio Ootaguro , Takayoshi Shimazawa , Kazuhiko Tachibana , Shin'ichi Kawakami , Seiji Norimatsu , Fujio Ishihara , Toshinori Sato , Hiroaki Murakami , Nobuhiro Ide , Yukio Endo , Akira Aono , Atsushi Kunimatsu 300MHz design methodology of VU for emotion synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Norman Kojima , Yukiko Parameswar , Christian Klingner , Yukio Ohtaguro , Masataka Matsui , Shigeaki Iwasa , Tatsuo Teruyama , Takayoshi Shimazawa , Hideki Takeda , Kouji Hashizume , Haruyuki Tago , Masaaki Yamada Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Fujio Ishihara , Christian Klinger , Ken-ichi Agawa Clock design of 300MHz 128-bit 2-way superscalar microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Masaharu Imai , Gary Smith , Steven Schulz , Karen Bartleson , Daniel Gajski , Wolfgang Rosenstiel , Peter Flake , Hiroto Yasuura One language or more?: how can we design an SoC at a system level? [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Liang Wu , Xiao-Long Yuan , David Ihsin Cheng Circuit partitioning with coupled logic restructuring techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov Improved algorithms for hypergraph bipartitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Maogang Wang , Sung Lim , Jason Cong , Majid Sarrafzadeh Multi-way partitioning using bi-partition heuristics. [Citation Graph (0, 0)][DBLP ] Conf ] 