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Asia and South Pacific Design Automation Conference (ASP-DAC) (aspdac)
2001 (conf/aspdac/2001)

  1. Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera
    A vector-pipeline DSP for low-rate videophones. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:1-2 [Conf]
  2. Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
    A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:3-4 [Conf]
  3. Yasuo Arai
    Multi-hit time-to-digital converter VLSI for high-energy physics experiments. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:5-6 [Conf]
  4. Mitsuru Yamada, Akinori Nishihara
    A high-speed FIR digital filter with CSD coefficients implemented on FPGA. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:7-8 [Conf]
  5. Yong-Ha Park, Seon-Ho Han, Hoi-Jun Yoo
    Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:9-10 [Conf]
  6. Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
    A dynamically reconfigurable hardware-based cipher chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:11-12 [Conf]
  7. Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata
    Test circuits for substrate noise evaluation in CMOS digital ICs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:13-14 [Conf]
  8. Roberto Y. Omaki, Yu Dong, Morgan Hirosuke Miki, Makoto Furuie, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa
    Realtime wavelet video coder based on reduced memory accessing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:15-16 [Conf]
  9. Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano
    A prototype chip of multicontext FPGA with DRAM for virtual hardware. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:17-18 [Conf]
  10. Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok
    A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:19-20 [Conf]
  11. Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada
    A smart position sensor for 3-D measurement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:21-22 [Conf]
  12. Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen
    Parameterized MAC unit implementation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:23-24 [Conf]
  13. Toshiyuki Nozawa, Makoto Imai, Masanori Fujibayashi, Tadahiro Ohmi
    A parallel vector quantization processor featuring an efficient search algorithm for real-time motion picture compression. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:25-26 [Conf]
  14. Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae
    An 8-b nRERL microprocessor for ultra-low-energy applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:27-28 [Conf]
  15. Chung-Jr Lian, Liang-Gee Chen, Hao-Chieh Chang, Yung-Chi Chang
    Design and implementation of JPEG encoder IP core. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:29-30 [Conf]
  16. Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
    A real-time 64-monosyllable recognition LSI with learning mechanism. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:31-32 [Conf]
  17. Ing-Jer Huang, Hsin-Ming Chen, Chung-Fu Kao
    Reusable embedded in-circuit emulator. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:33-34 [Conf]
  18. Satoshi Sakaidani, Naoto Miyamoto, Tadahiro Ohmi
    Flexible processor based on full-adder/ d-flip-flop merged module. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:35-36 [Conf]
  19. Takanori Okuma, Koji Hashimoto, Kazuaki Murakami
    Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:37-38 [Conf]
  20. D. Miyawaki, S. Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, M. Suetake, Michiko Miura-Mattausch, Shigetaka Kumashiro, T. Yamaguchi, K. Yamashita, N. Nakayama
    Correlation method of circuit-performance and technology fluctuations for improved design reliability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:39-44 [Conf]
  21. Zhao Li, Xiao-Feng Xie, Wenjun Zhang, Zhilian Yang
    Realization of semiconductor device synthesis with the parallel genetic algorithm. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:45-49 [Conf]
  22. Martin R. Frerichs
    Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talk. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:50-56 [Conf]
  23. Jianwen Zhu, Daniel Gajski
    Compiling SpecC for simulation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:57-62 [Conf]
  24. Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya
    Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:63-68 [Conf]
  25. Kjetil Svarstad, Nezih Ben-Fredj, Gabriela Nicolescu, Ahmed Amine Jerraya
    A higher level system communication model for object-oriented specification and design of embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:69-77 [Conf]
  26. Chanik Park, Sungchan Kim, Soonhoi Ha
    A dataflow specification for system level synthesis of 3D graphics applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:78-84 [Conf]
  27. Christoph Scholl, Bernd Becker, Andreas Brogle
    The multiple variable order problem for binary decision diagrams: theory and practical application. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:85-90 [Conf]
  28. Wolfgang Günther, Andreas Hett, Bernd Becker
    Application of linearly transformed BDDs in sequential verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:91-96 [Conf]
  29. Christoph Meinel, Christian Stangier
    A new partitioning scheme for improvement of image computation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:97-102 [Conf]
  30. Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
    An efficient design-for-verification technique for HDLs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:103-108 [Conf]
  31. Paul-Peter Sotiriadis, Anantha Chandrakasan
    Reducing bus delay in submicron technology using coding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:109-114 [Conf]
  32. Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
    Optimal spacing and capacitance padding for general clock structures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:115-119 [Conf]
  33. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Provably good global buffering by multi-terminal multicommodity flow approximation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:120-125 [Conf]
  34. LiYi Lin, Yi-Yu Liu, TingTing Hwang
    A construction of minimal delay Steiner tree using two-pole delay model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:126-132 [Conf]
  35. Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky
    New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:133-138 [Conf]
  36. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
    Hierarchical dummy fill for process uniformity. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:139-144 [Conf]
  37. Sani R. Nassif
    Modeling and forecasting of manufacturing variations (embedded tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:145-150 [Conf]
  38. Takashi Kambe, Akihisa Yamada, Koichi Nishida, Kazuhisa Okada, Mitsuhisa Ohnishi, Andrew Kay, Paul Boca, Vince Zammit, Toshio Nomura
    A C-based synthesis system, Bach, and its application (invited talk). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:151-155 [Conf]
  39. Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    Area/delay estimation for digital signal processor cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:156-161 [Conf]
  40. Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu
    An RTL design-space exploration method for high-level applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:162-168 [Conf]
  41. Jiunn-Chern Chen, Yirng-An Chen
    Equivalence checking of integer multipliers. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:169-174 [Conf]
  42. G. Subash Chandar, S. Vaideeswaran
    Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:175-180 [Conf]
  43. Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee
    An efficient solution to the storage correspondence problem for large sequential circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:181-186 [Conf]
  44. Yih-Chih Chou, Youn-Long Lin
    A 3-step approach for performance-driven whole-chip routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:187-191 [Conf]
  45. Hai Zhou, Narendra V. Shenoy, William Nicholls
    Efficient minimum spanning tree construction without Delaunay triangulation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:192-197 [Conf]
  46. Minghorng Lai, D. F. Wong
    Memory-efficient interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:198-202 [Conf]
  47. Payam Heydari, Massoud Pedram
    Balanced truncation with spectral shaping for RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:203-208 [Conf]
  48. Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney
    An optimum fitting algorithm for generation of reduced-order models. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:209-213 [Conf]
  49. Zhaozhi Yang, Zeyi Wang, Shuzhou Fang
    A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:214-218 [Conf]
  50. Tsutomu Sasao, Jon T. Butler
    On the minimization of SOPs for bi-decomposition functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:219-224 [Conf]
  51. Jian Qiao, Makoto Ikeda, Kunihiro Asada
    Finding an optimal functional decomposition for LUT-based FPGA synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:225-230 [Conf]
  52. Kenneth Yan
    Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:231-234 [Conf]
  53. Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin
    A new techology mapping for CPLD under the time constraint. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:235-238 [Conf]
  54. Massoud Pedram
    Power optimization and management in embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:239-244 [Conf]
  55. Wei-Chung Cheng, Massoud Pedram
    Low power techniques for address encoding and memory allocation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:245-250 [Conf]
  56. Vishnu Swaminathan, Krishnendu Chakrabarty
    Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:251- [Conf]
  57. Joep L. W. Kessels, Ad M. G. Peeters
    The tangram framework (embedded tutorial): asynchronous circuits for low power. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:255-260 [Conf]
  58. Jeong-Gun Lee, Euiseok Kim, Dong-Ik Lee
    Imprecise data computation for high performance asynchronous processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:261-266 [Conf]
  59. Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
    Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:267-268 [Conf]
  60. Kuniyuki Tani, Norihiro Nikai, Atsushi Wada, Tetsuro Sawai
    A pipelined ADC macro design for multiple applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:269-274 [Conf]
  61. Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera
    A dynamically phase adjusting PLL with a variable delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:275-280 [Conf]
  62. Florin Balasa
    Device-level placement for analog layout: an opportunity for non-slicing topological representations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:281-286 [Conf]
  63. Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang
    A mixed-signal simulator for VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:287-292 [Conf]
  64. Shekhar Borkar
    Low power design challenges for the decade (invited talk). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:293-296 [Conf]
  65. Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka
    An on-chip 96.5% current efficiency CMOS linear regulator. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:297-301 [Conf]
  66. Vasily G. Moshnyaga
    Reducing cache engery through dual voltage supply. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:302-305 [Conf]
  67. Tony Givargis, Frank Vahid, Jörg Henkel
    Trace-driven system-level power evaluation of system-on-a-chip peripheral cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:306-312 [Conf]
  68. Shi-Yu Huang
    Towards the logic defect diagnosis for partial-scan designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:313-318 [Conf]
  69. Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri
    Cellular automata as a built in self test structure. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:319-324 [Conf]
  70. Ching-Hong Tsai, Cheng-Wen Wu
    Processor-programmable memory BIST for bus-connected embedded memories. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:325-330 [Conf]
  71. Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara
    A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:331-334 [Conf]
  72. Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng
    Timed circuits: a new paradigm for high-speed design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:335-340 [Conf]
  73. Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff
    Conformance and mirroring for timed asychronous circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:341-346 [Conf]
  74. Xiaohua Kong, Radu Negulescu
    Formal verification of pulse-mode asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:347-352 [Conf]
  75. Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui
    A statistical static timing analysis considering correlations between delays. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:353-358 [Conf]
  76. Masanori Hashimoto, Hidetoshi Onodera
    Post-layout transistor sizing for power reduction in cell-based design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:359-365 [Conf]
  77. Wenjian Yu, Zeyi Wang
    An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:366-372 [Conf]
  78. Jason Cong, David Zhigang Pan, Prasanna V. Srinivas
    Improved crosstalk modeling for noise constrained interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:373-378 [Conf]
  79. Hao Ji, Anirudh Devgan, Wayne Wei-Ming Dai
    KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:379-384 [Conf]
  80. Liang Yin, Lei He
    An efficient analytical model of coupled on-chip RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:385-390 [Conf]
  81. Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu
    RSA cryptosystem design based on the Chinese remainder theorem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:391-395 [Conf]
  82. Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
    Speech recognition chip for monosyllables. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:396-399 [Conf]
  83. Frank Gilbert, Alexander Worm, Norbert Wehn
    Low power implementation of a turbo-decoder on programmable architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:400-403 [Conf]
  84. Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun-Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee
    Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:404-408 [Conf]
  85. Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi
    New directions in compiler technology for embedded systems (embedded tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:409-414 [Conf]
  86. Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel
    Optimized address assignment for DSPs with SIMD memory accesses. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:415-420 [Conf]
  87. Partha S. Roop, Arcot Sowmya, S. Ramesh
    A formal approach to component based development of synchronous programs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:421-424 [Conf]
  88. Hiroto Kagotani, Takuji Okamoto, Takashi Nanya
    Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:425-430 [Conf]
  89. Ross Smith, Michiel M. Ligthart
    High-level design for asynchronous logic. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:431-436 [Conf]
  90. Nattha Sretasereekul, Takashi Nanya
    Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:437-442 [Conf]
  91. Andrew B. Kahng
    Design technology productivity in the DSM era (invited talk). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:443-448 [Conf]
  92. Flavius Gruian, Krzysztof Kuchcinski
    LEneS: task scheduling for low-energy systems using variable supply voltage processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:449-455 [Conf]
  93. Tohru Ishihara, Kunihiro Asada
    A system level memory power optimization technique using multiple supply and threshold voltages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:456-461 [Conf]
  94. Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung
    Low-power high-level synthesis using latches. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:462-466 [Conf]
  95. José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
    Functional extension of structural logic optimization techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:467-472 [Conf]
  96. Chin Ngai Sze, Yu-Liang Wu
    Improved alternative wiring scheme applying dominator relationship. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:473-478 [Conf]
  97. Andreas G. Veneris, Magdy S. Abadir, Ivor Ting
    Design rewiring based on diagnosis techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:479-484 [Conf]
  98. Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta
    Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:485-491 [Conf]
  99. Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee
    A computer aided engineering system for memory BIST. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:492-495 [Conf]
  100. Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty
    Synthesis of single-output space compactors with application to scan-based IP cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:496-502 [Conf]
  101. Wing Seung Yuen, Fung Yu Young
    Slicing floorplan with clustering constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:503-508 [Conf]
  102. Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    VLSI floorplanning with boundary constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:509-514 [Conf]
  103. Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang
    Module placement with boundary constraints using the sequence-pair representation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:515-520 [Conf]
  104. Xiaoping Tang, D. F. Wong
    FAST-SP: a fast algorithm for block placement based on sequence pair. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:521-526 [Conf]
  105. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
    Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:527-532 [Conf]
  106. Youxin Gao, D. F. Wong
    A fast and accurate delay estimation method for buffered interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:533-538 [Conf]
  107. Denis Deschacht, Grégory Servel
    On-chip interconnections: impact of adjacent lines on timing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:539-544 [Conf]
  108. Seung-Ho Jung, Jong-Humn Baek, Seok-Yoon Kim
    Short circuit power estimation of static CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:545-550 [Conf]
  109. Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki
    A novel network node architecture for high performance and function flexibility. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:551-557 [Conf]
  110. Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man
    Virtual Java/FPGA interface for networked reconfiguration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:558-563 [Conf]
  111. Reiner W. Hartenstein
    Coarse grain reconfigurable architecture (embedded tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:564-570 [Conf]
  112. Rajeev Murgai
    Efficient global fanout optimization algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:571-576 [Conf]
  113. Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication in technology independent phase. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:577-582 [Conf]
  114. Shi-Yu Huang
    On speeding up extended finite state machines using catalyst circuitry. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:583-588 [Conf]
  115. I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
    Integrated power supply planning and floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:589-594 [Conf]
  116. Amir H. Ajami, Massoud Pedram
    Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:595-600 [Conf]
  117. Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu
    VLSI block placement using less flexibility first principles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:601-604 [Conf]
  118. Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao
    A new congestion-driven placement algorithm based on cell inflation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:605-608 [Conf]
  119. Yumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen
    Cell selection from technology libraries for minimizing power. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:609-614 [Conf]
  120. Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler
    Low power optimization technique for BDD mapped circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:615-621 [Conf]
  121. Youngtae Kim, Taewhan Kim
    Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:622-628 [Conf]
  122. Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh
    RPack: routability-driven packing for cluster-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:629-634 [Conf]
  123. Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang
    Power minization in LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:635-640 [Conf]
  124. Hongbing Fan, Jiping Liu, Yu-Liang Wu
    Combinatorial routing analysis and design of universal switch blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:641-644 [Conf]
  125. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
    Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:645-648 [Conf]
  126. Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai
    Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:649-654 [Conf]
  127. Maria-Cristina V. Marinescu, Martin C. Rinard
    High-level specification and efficient implementation of pipelined circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:655-661 [Conf]
  128. Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi
    High-level synthesis under multi-cycle interconnect delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:662- [Conf]
NOTICE1
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NOTICE2
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