Conferences in DBLP
Biswadip Mitra Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuo Yano LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration Era. [Citation Graph (0, 0)][DBLP ] Conf ] Aart J. de Geus Electronic Industry on Fire: How to Survive and Thrive. [Citation Graph (0, 0)][DBLP ] Conf ] Martin F. H. Schuurmans Digital Watermarking. [Citation Graph (0, 0)][DBLP ] Conf ] Subir K. Roy , S. Ramesh , Supratik Chakraborty , Tsuneo Nakata , Sreeranga P. Rajan Functional Verification of System on Chips-Practices, Issues and Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Pieter van der Wolf , W. M. Kruijtzer , Jos T. J. van Eijndhoven T2: System-Level Design of Embedded Media Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Rusu , Manoj Sachdev , Christer Svensson , B. Nauta T3: Trends and Challenges in VLSI Technology Scaling towards 100nm. [Citation Graph (0, 0)][DBLP ] Conf ] M. V. Atre , P. S. Subramanian , H. Narayanan T4: Mathematical Methods in VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Michael L. Bushnell T5: Electronic Testing for SOC Designers. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Lavagno , Sujit Dey , Rajesh Gupta Specification, Modeling and Design Tools for System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] R. Lal , P. R. Apte , K. N. Bhat , G. Bose , S. Chandra , D. K. Sharma T7: MEMS: Technology, Design, CAD and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jordi Cortadella , Alexandre Yakovlev , Jim D. Garside T8: Logic Design of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David Duarte , Yuh-Fang Tsai , Narayanan Vijaykrishnan , Mary Jane Irwin Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Wenjie Jiang , Vivek Tiwari , Erik de la Iglesia , Amit Sinha Topological Analysis for Leakage Prediction of Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Kumar , C. P. Ravikumar Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Li , Lei He , Kewal K. Saluja Estimation of Maximum Power-up Current. [Citation Graph (0, 0)][DBLP ] Conf ] Joong-Ho Kim , Erdem Matoglu , Jinwoo Choi , Madhavan Swaminathan Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method. [Citation Graph (0, 0)][DBLP ] Conf ] Seung Hoon Choi , Bipul Chandra Paul , Kaushik Roy Dynamic Noise Analysis with Capacitive and Inductive Coupling. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Nagata , Youichi Nishimori , Takashi Morie , Atsushi Iwata , Yoshitaka Murasaka Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. [Citation Graph (0, 0)][DBLP ] Conf ] Kanak Agarwal , Yu Cao , Takashi Sato , Dennis Sylvester , Chenming Hu Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Rupesh S. Shelar , Sachin S. Sapatnekar An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Saito , Takashi Nanya , Alex Kondratyev Design of Asynchronous Controllers with Delay Insensitive Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Debasis Samanta , Ajit Pal , Nishant Sinha Synthesis of High Performance Low Power Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vineet Sahula , C. P. Ravikumar , D. Nagchoudhuri Improvement of ASIC Design Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Haris Lekatsas , Jörg Henkel ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Rung-Bin Lin , Chi-Ming Tsai Weight-Based Bus-Invert Coding for Low-Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Chung Cheng , Jian-Lin Liang , Massoud Pedram Software-Only Bus Encoding Techniques for an Embedded System. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Heydari , Massoud Pedram Interconnect Energy Dissipation in High-Speed ULSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Poras T. Balsara , Cyrus Cantrell Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. [Citation Graph (0, 0)][DBLP ] Conf ] P. K. Datta , S. Sanyal , D. Bhattacharya Losses in Multilevel Crossover in VLSI Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Qinwei Xu , Pinaki Mazumder Rational ABCD Modeling of High-Speed Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Hsing Cheng , Shun-Wen Cheng Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Hafizur Rahaman , Debesh K. Das , Bhargab B. Bhattacharya A New Synthesis of Symmetric Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Yoshida , Hiroaki Yamaoka , Makoto Ikeda , Kunihiro Asada Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. [Citation Graph (0, 0)][DBLP ] Conf ] D. Sarkar Register Transfer Operation Analysis during Data Path Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Murugavel , N. Ranganathan A Real Delay Switching Activity Simulator based on Petri net Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjukta Bhanja , N. Ranganathan Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Debasis Samanta , Ajit Pal Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Eric F. Weglarz , Kewal K. Saluja , Mikko H. Lipasti Minimizing Energy Consumption for High-Performance Processing. [Citation Graph (0, 0)][DBLP ] Conf ] A. B. Bhattacharyya , Shrutin Ulman PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Lee , Shinji Ito , Takeaki Hashimoto , Tomomasa Touma , Junji Sato , Goichi Yokomizo A Parallel and Accelerated Circuit Simulator with Precise Accuracy. [Citation Graph (0, 0)][DBLP ] Conf ] Srinath R. Naidu Timing Yield Calculation Using an Impulse-train Approach. [Citation Graph (0, 0)][DBLP ] Conf ] H. C. Srinivasaiah , Navakanta Bhat Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal P. Bhatt , M. Balakrishnan , Anshul Kumar Exploring the Number of Register Windows in ASIP Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Schliebusch , Andreas Hoffmann , Achim Nohl , Gunnar Braun , Heinrich Meyr Architecture Implementation Using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Ascia , Vincenzo Catania , Maurizio Palesi A Framework for Design Space Exploration of Parameterized VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] S. Chakraverty , C. P. Ravikumar , D. Roy Choudhuri An Evolutionary Scheme for Cosynthesis of Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kanishka Lahiri , Sujit Dey , Debashis Panigrahi , Anand Raghunathan Battery-Driven System Design: A New Frontier in Low Power Design. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Muroyama , Akihiko Hyodo , Hiroto Yasuura , Tohru Ishihara A Power Minimization Technique for Arithmetic Circuits by Cell Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Yunsi Fei , Niraj K. Jha Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Tohru Ishihara , Kunihiro Asada An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Victor M. DeLaLuz , Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin , Anand Sivasubramaniam , Ibrahim Kolcu Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. [Citation Graph (0, 0)][DBLP ] Conf ] S. Natarajan , A. Marshall Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Vipul Singhal , C. B. Keshav , K. G. Surnanth , P. R. Suresh Transistor Flaring in Deep Submicron-Design Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Shuzhou Fang , Zeyi Wang , Xianlong Hong A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. [Citation Graph (0, 0)][DBLP ] Conf ] Q. Su , Venkataramanan Balakrishnan , Cheng-Kok Koh Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Maryam Shojaei Baghini , Madhav P. Desai Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. [Citation Graph (0, 0)][DBLP ] Conf ] P. Klapproth Embedded Tutorial: General Architectural Concepts for IP Core Re-Use. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasan Dasasathyan , Rajesh Radhakrishnan , Ranga Vemuri Framework for Synthesis of Virtual Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Junyu Peng , Samar Abdi , Daniel Gajski Automatic Model Refinement for Fast Architecture Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Barat , Murali Jayapala , Pieter Op de Beeck , Geert Deconinck , K. U. Leuven Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Li Shang , Niraj K. Jha Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Sugawara , Yoshikazu Miyanaga , Norinobu Yoshida A Design of Analog C-Matrix Circuits used for Signal/Data Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Debapriya Sahu A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Biranchinath Sahu , Aloke K. Dutta Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Lienig , Goeran Jerke , Thorsten Adler Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Chen , Massoud Pedram , Premal Buch Buffered Routing Tree Construction Under Buffer Placement Blockages. [Citation Graph (0, 0)][DBLP ] Conf ] Yuchun Ma , Xianlong Hong , Sheqin Dong , Yici Cai , Chung-Kuan Cheng , Jun Gu Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Ming Tsai , Kun-Tien Kuo , Chyi-Hui Hong , Rung-Bin Lin An Adaptive Interconnect-Length Driven Placer. [Citation Graph (0, 0)][DBLP ] Conf ] Stelian Alupoaei , Srinivas Katkoori Net Clustering Based Macrocell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Raghunathan , Mani B. Srivastava , Milos D. Ercegovac , Anand Raghunathan High-Level Synthesis with SIMD Units. [Citation Graph (0, 0)][DBLP ] Conf ] J. Ramanujam , Sandeep Deshpande , Jinpyo Hong , Mahmut T. Kandemir A Heuristic for Clock Selection in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Krishna Sekar , Vamsi Boppana Design for Verification at the Register Transfer Level. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriela Nicolescu , S. Martinez , Lobna Kriaa , Wassim Youssef , Sungjoo Yoo , Benoît Charlot , Ahmed Amine Jerraya Application of Multi-domain and Multi-language Cosimulation To an Optical MEM Switch Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kavish Seth , S. Srinivasan VLSI Implementation of 2-D DWT/IDWT Cores using 9/7-tap filter banks based on the Non-expansive Symmetric Extension Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Hak-soo Yu , Jacob A. Abraham An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Shobha Singh , Shamsi Azmi , Nutan Aarawal , Penaka Phani , Ansuman Rout Architecture and Design of a High Performance SRAM for SoC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jinku Choi , Masao Yanagisawa , Tatsuo Ohtsuki , Nozomu Togawa VLSI Architecture for a Flexible Motion Estimation with Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhat Mishra , Ashok Halambi , Peter Grun , Nikil D. Dutt , Alexandru Nicolau , Hiroyuki Tomiyama Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language. [Citation Graph (0, 0)][DBLP ] Conf ] Yukiko Kubo , Shigetoshi Nakatake , Yoji Kajitani , Masahiro Kawakita Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Jingyu Xu , Xianlong Hong , Tong Jing , Yici Cai , Jun Gu An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Yoshida , Motohiro Sera , Masao Kubo , Masahiro Fujita Simultaneous Circuit Transformation and Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Chunhong Chen Probabilistic Analysis of Rectilinear Steiner Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyou Zhao , Kaushik Oy , Cheng-Kok Koh Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Hailong Cui , Sharad C. Seth , Shashank K. Mehta A Novel Method to Improve the Test Efficiency of VLSI Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Koranne On Test Scheduling for Core-Based SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Sudhakar M. Reddy , Nilanjan Mukherjee , Chien-Chung Tsai , Omer Samman , Yahya Zaidan , Yanping Zhang , Wu-Tung Cheng Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Katarzyna Radecka , Zeljko Zilic Identifying Redundant Wire Replacements for Synthesis and Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Albert E. Casavant , Pranav Ashar , Akira Mukaiyama , Kazutoshi Wakabayashi , X. G. Liu Property-Specific Testbench Generation for Guided Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Murali Mohan , Rohini Krishnan , Anshul Kumar , M. Balakrishnan A New Divide and Conquer Method for Achieving High Speed Division in Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Han , Sri Parameswaran Swasad: An Asic Design For High Speed Dna Sequence Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Palkovic , Miguel Miranda , Kristof Denolf , Peter Vos , Francky Catthoor Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Panigrahi , Clark N. Taylor , Sujit Dey A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Qinwei Xu , Pinaki Mazumder Efficient Macromodeling for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Silke Salewski , Erich Barke An Upper Bound for 3D Slicing Floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Jingcao Hu , Yangdong Deng , Radu Marculescu System-Level Point-to-Point Communication Synthesis Using Floorplanning Information. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Albrecht , Andrew B. Kahng , Ion I. Mandoiu , Alexander Zelikovsky Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Chang Kim , Kewal K. Saluja , Vishwani D. Agrawal Multiple Faults: Modeling, Simulation and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Subhayu Basu , Debdeep Mukhopadhyay , Dipanwita Roy Chowdhury , Indranil Sengupta , Sudipta Bhawmik Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. [Citation Graph (0, 0)][DBLP ] Conf ] Nadir Z. Basturkmen , Sudhakar M. Reddy , Janusz Rajski Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Sornavalli Ramanathan , Rituparna Mandal Low Power Solution for Wireless Applications. [Citation Graph (0, 0)][DBLP ] Conf ] J. Ramanujam , Satish Krishnamurthy , Jinpyo Hong , Mahmut T. Kandemir Address Code and Arithmetic Optimizations for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yong-Ha Park , Hoi-Jun Yoo , Jeonghoon Kook Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-chip (SoC) Applications. [Citation Graph (0, 0)][DBLP ] Conf ] N. E. Crosbie , Mahmut T. Kandemir , Ibrahim Kolcu , J. Ramanujam , Alok N. Choudhary Strategies for Improving Data Locality in Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Shankar Balachandran , PariVallal Kannan , Dinesh Bhatia On Routing Demand and Congestion Estimation for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Supratik Chakraborty , Rajeev Murgai Layout-driven Timing Optimization by Generalized De Morgan Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Rituparna Mandal , Dibyendu Goswami , Arup Dash Reducing Library Development Cycle Time through an Optimum Layout Create Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Evangeline F. Y. Young , M. L. Ho , Chris C. N. Chu A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. [Citation Graph (0, 0)][DBLP ] Conf ] Samir Roy , Biplab K. Sikdar , Monalisa Mukherjee , Debesh K. Das Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Sugihara , Hiroto Yasuura Optimization of Test Accesses with a Combined BIST and External Test Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Niloy Ganguly , Biplab K. Sikdar , Parimal Pal Chaudhuri Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP ] Conf ] Dexin Li , Pai H. Chou , Nader Bagherzadeh Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Anupam Datta , Sidharth Choudhury , Anupam Basu Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks. [Citation Graph (0, 0)][DBLP ] Conf ] Weidong Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha Input Space Adaptive Embedded Software Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jiong Luo , Niraj K. Jha Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Malay K. Ganai , Adnan Aziz Improved SAT-based Bounded Reachability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Pallab Dasgupta , Arindam Chakrabarti , P. P. Chakrabarti Open Computation Tree Logic for Formal Verification of Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Raik Brinkmann , Rolf Drechsler RTL-Datapath Verification using Integer Linear Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Yozo Nakayama , Toshiya Mima Verification of an Industrial CC-NUMA Server. [Citation Graph (0, 0)][DBLP ] Conf ] Sagar S. Sabade , Hank Walker Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Rahul Kumar Divide-and-Conquer IDDQ Testing for Core-based System Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Yun Shao , Sudhakar M. Reddy , Irith Pomeranz Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. [Citation Graph (0, 0)][DBLP ] Conf ] Baidya Nath Ray , Parimal Pal Chaudhuri , Prasanta Kumar Nandi Test Solution For OTA Based Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjeev Patel Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Ranjit Yashwante , Bhalchandra Jahagirdar IEEE 1394a_2000 Physical Layer ASIC. [Citation Graph (0, 0)][DBLP ] Conf ] T. Datta , C. S. Muralidharan Definition, Design and Development of the IXE2424 Network Switch/Router ASIC. [Citation Graph (0, 0)][DBLP ] Conf ] 