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Asia and South Pacific Design Automation Conference (ASP-DAC) (aspdac)
2004 (conf/aspdac/2004)

  1. Rudy Lauwereins
    System level design technology for realizing an ambient intelligent environment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:1-3 [Conf]
  2. Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefan Steinke, Urs Helmig
    Fast, predictable and low energy memory references through architecture-aware compilation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:4-11 [Conf]
  3. Wolfgang Nebel
    Predictable design of low power systems by pre-implementation estimation and optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:12-17 [Conf]
  4. Ahmed Amine Jerraya
    EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:18- [Conf]
  5. Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
    Abstraction and optimization of consistent floorplanning with pillar block constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:19-24 [Conf]
  6. Xuliang Zhang, Yoji Kajitani
    Space-planning: placement of modules with controlled empty area by single-sequence. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:25-30 [Conf]
  7. Jacob R. Minz, Sung Kyu Lim
    Layer assignment for reliable system-on-package. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:31-37 [Conf]
  8. Xiaoping Tang, Martin D. F. Wong
    On handling arbitrary rectilinear shape constraint. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:38-41 [Conf]
  9. Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang
    Robust fixed-outline floorplanning through evolutionary search. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:42-44 [Conf]
  10. Jian Wang, Jun Tao, Xuan Zeng, Charles Chiang, Dian Zhou
    Analog circuit behavioral modeling via wavelet collocation method with auto-companding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:45-50 [Conf]
  11. Ewout Martens, Georges G. E. Gielen
    High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:51-56 [Conf]
  12. Payam Heydari
    High-frequency noise in RF active CMOS mixers. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:57-60 [Conf]
  13. Rasit Onur Topaloglu, Alex Orailoglu
    On mismatch in the deep sub-micron era - from physics to circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:62-67 [Conf]
  14. Deming Chen, Jason Cong
    Register binding and port assignment for multiplexer optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:68-73 [Conf]
  15. Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    A thread partitioning algorithm in low power high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:74-79 [Conf]
  16. Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura
    Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:80-85 [Conf]
  17. Hashem Hashemi Najaf-abadi
    A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:86-91 [Conf]
  18. Kai Yang, Kwang-Ting Cheng, Li-C. Wang
    TranGen: a SAT-based ATPG for path-oriented transition faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:92-97 [Conf]
  19. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    Longest path selection for delay test under process variation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:98-103 [Conf]
  20. Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu
    SRAM delay fault modeling and test algorithm development. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:104-109 [Conf]
  21. Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri
    An efficient design of non-linear CA based PRPG for VLSI circuit testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:110-112 [Conf]
  22. Andrew B. Kahng, Sherief Reda
    Combinatorial group testing methods for the BIST diagnosis problem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:113-116 [Conf]
  23. Yukikazu Nakamoto
    Toward mobile phone Linux. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:117-124 [Conf]
  24. Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow
    Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:125-130 [Conf]
  25. Alexander Maxiaguine, Simon Künzli, Samarjit Chakraborty, Lothar Thiele
    Rate analysis for streaming applications with on-chip buffer constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:131-136 [Conf]
  26. Mongkol Ekpanyapong, Sung Kyu Lim
    Performance-driven global placement via adaptive network characterization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:137-142 [Conf]
  27. Bernd Obermeier, Frank M. Johannes
    Temperature-aware global placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:143-148 [Conf]
  28. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:149-154 [Conf]
  29. Keoncheol Shin, Taewhan Kim
    An integrated approach to timing-driven synthesis and placement of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:155-158 [Conf]
  30. Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao
    Layer assignment for crosstalk risk minimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:159-162 [Conf]
  31. Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi
    CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:163-168 [Conf]
  32. Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y. Wong
    NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:169-174 [Conf]
  33. Praveen Ghanta, Zheng Li, Jaijeet S. Roychowdhury
    Analytical expressions for phase noise eigenfunctions of LC oscillators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:175-180 [Conf]
  34. Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra
    Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:181-185 [Conf]
  35. Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura
    Timing optimization by replacing flip-flops to latches. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:186-191 [Conf]
  36. Hiroyuki Higuchi, Yusuke Matsunaga
    Enhancing the performance of multi-cycle path analysis in an industrial setting. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:192-197 [Conf]
  37. Noureddine Chabini, Wayne Wolf
    An approach for reducing dynamic power consumption in synchronous sequential digital designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:198-204 [Conf]
  38. Yen-Te Ho, TingTing Hwang
    Low power design using dual threshold voltage. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:205-208 [Conf]
  39. Chang Woo Kang, Ali Iranli, Massoud Pedram
    Technology mapping and packing for coarse-grained, anti-fuse based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:209-211 [Conf]
  40. Ozgur Sinanoglu, Alex Orailoglu
    Efficient RT-level fault diagnosis methodology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:212-217 [Conf]
  41. Alexander Smith, Andreas G. Veneris, Anastasios Viglas
    Design diagnosis using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:218-223 [Conf]
  42. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:224-229 [Conf]
  43. Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase
    Test data compression technique using selective don't-care identification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:230-233 [Conf]
  44. Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan
    Re-configurable embedded core test protocol. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:234-237 [Conf]
  45. C. Schulz-Key, Markus Winterholer, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel
    Object-oriented modeling and synthesis of SystemC specifications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:238-243 [Conf]
  46. Robertas Damasevicius, Vytautas Stuikys
    Application of UML for hardware design based on design process model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:244-249 [Conf]
  47. Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    A cosynthesis algorithm for application specific processors with heterogeneous datapaths. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:250-255 [Conf]
  48. Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada
    Design methodology for SoC arthitectures based on reusable virtual cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:256-262 [Conf]
  49. Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng
    A multiple level network approach for clock skew minimization with process variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:263-268 [Conf]
  50. Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
    Layout techniques for on-chip interconnect inductance reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:269-273 [Conf]
  51. Zhong Wang, Jianwen Zhu
    Piecewise quadratic waveform matching with successive chord iteration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:274-279 [Conf]
  52. Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
    Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:280-283 [Conf]
  53. Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy
    Adaptive supply voltage technique for low swing interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:284-287 [Conf]
  54. Kyeong-Sik Min, Young-Hee Kim, Daejeong Kim, Dong Myeong Kim, Jin-Hong Ahn
    A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:288-291 [Conf]
  55. Jianhua Gan, Shouli Yan, Jacob A. Abraham
    Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:292-297 [Conf]
  56. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    Jitter spectral extraction for multi-gigahertz signal. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:298-303 [Conf]
  57. Quoc-Hoang Duong, Sang-Gug Lee
    A 35 dB-linear exponential function generator for VGA and AGC applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:304-306 [Conf]
  58. Simon C. Li, Vincent Chia-Chang Lin
    A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:307-309 [Conf]
  59. Miroslav N. Velev
    Efficient translation of boolean formulas to CNF in formal verification of microprocessors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:310-315 [Conf]
  60. Miroslav N. Velev
    Using positive equality to prove liveness for pipelined microprocessors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:316-321 [Conf]
  61. Samar Abdi, Daniel Gajski
    On deriving equivalent architecture model from system specification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:322-327 [Conf]
  62. Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou
    On compliance test of on-chip bus for SOC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:328-333 [Conf]
  63. Kazumi Hatayama, Rochit Rajsuman
    Opportunities with the open architecture test system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:334- [Conf]
  64. Rochit Rajsuman
    New opportunities with the open architecture test system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:335- [Conf]
  65. Yasumasa Nishimura
    Open architecture tester: what is a key issue of OAT? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:336- [Conf]
  66. Srimat T. Chakradhar
    Open architecture test system: not why but when! [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:337-340 [Conf]
  67. Adi Merschon
    New opportunities with the open architecture test system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:341- [Conf]
  68. Dennis M. Petrich
    Signal integrity analysis in the open architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:342- [Conf]
  69. Tetsuo Tada
    Opportunities with the open architecture test system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:343- [Conf]
  70. Kazutoshi Wakabayashi
    C-based behavioral synthesis and verification analysis on industrial design examples. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:344-348 [Conf]
  71. Chris Sullivan, Alex Wilson, Stephen Chappell
    Using C based logic synthesis to bridge the productivity gap. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:349-354 [Conf]
  72. Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
    A place and route aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:355-360 [Conf]
  73. Sampath Dechu, Zion Cien Shen, Chris C. N. Chu
    An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:361-366 [Conf]
  74. Jun Chen, Lei He
    Modeling of coplanar waveguide for buffered clock tree. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:367-372 [Conf]
  75. Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya
    Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:373-379 [Conf]
  76. Venkata Syam P. Rapaka, Emil Talpes, Diana Marculescu
    Mixed-clock issue queue design for energy aware, high-performance cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:380-383 [Conf]
  77. G. Surendra, Subhasis Banerjee, S. K. Nandy
    Power-performance trade-off using pipeline delays. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:384-386 [Conf]
  78. Subhasis Banerjee, G. Surendra, S. K. Nandy
    Exploiting program execution phases to trade power and performance for media workload. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:387-389 [Conf]
  79. Subhasis Bhattacharjee, Dhiraj K. Pradhan
    LPRAM: a low power DRAM with testability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:390-393 [Conf]
  80. Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi
    Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:394-399 [Conf]
  81. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi
    Hierarchical extraction and verification of symmetry constraints for analog layout automation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:400-405 [Conf]
  82. Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
    Multi-level placement with circuit schema based clustering in analog IC layouts. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:406-411 [Conf]
  83. Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay
    Model checking on state transition diagram. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:412-417 [Conf]
  84. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
    Efficient reachability checking using sequential SAT. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:418-423 [Conf]
  85. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
    Exploiting state encoding for invariant generation in induction-based property checking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:424-429 [Conf]
  86. Xiaoping Tang, Martin D. F. Wong
    Tradeoff routing resource, runtime and quality in buffered routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:430-433 [Conf]
  87. Noriyuki Miura, Naoki Kato, Tadahiro Kuroda
    Practical methodology of post-layout gate sizing for 15% more power saving. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:434-437 [Conf]
  88. Chanseok Hwang, Massoud Pedram
    Interconnect design methods for memory design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:438-443 [Conf]
  89. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang
    Optimal planning for mesh-based power distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:444-449 [Conf]
  90. Yangdong (Steven) Deng, Wojciech Maly
    2.5D system integration: a design driven system implementation schema. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:450-455 [Conf]
  91. Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
    An HMAC processor with integrated SHA-1 and MD5 algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:456-458 [Conf]
  92. Frank Kienle, Norbert Wehn
    Design methodology for IRA codes. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:459-462 [Conf]
  93. Haobo Yu, Rainer Dömer, Daniel Gajski
    Embedded software generation from system level design languages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:463-468 [Conf]
  94. Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya
    Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:469-474 [Conf]
  95. Aviral Shrivastava, Nikil D. Dutt
    Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:475-477 [Conf]
  96. Yoonseo Choi, Taewhan Kim
    Memory access driven storage assignment for variables in embedded system design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:478-481 [Conf]
  97. Mitiko Miura-Mattausch
    MOSFET modeling for RF-CMOS design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:482-490 [Conf]
  98. Robert A. Mullen
    RF design methodologies bridging system-IC-module design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:491-498 [Conf]
  99. Haifeng Qian, Sachin S. Sapatnekar
    Hierarchical random-walk algorithms for power grid analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:499-504 [Conf]
  100. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
    A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:505-510 [Conf]
  101. Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda
    Large-scale linear circuit simulation with an inversed inductance matrix. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:511-516 [Conf]
  102. Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda
    DEPOGIT: dense power-ground interconnect architecture for physical design integrity. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:517-522 [Conf]
  103. Yusuke Oike, Makoto Ikeda, Kunihiro Asada
    Design of real-time VGA 3-D image sensor using mixed-signal techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:523-524 [Conf]
  104. Kun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen
    A bandwidth and memory efficient MPEG-4 shape encoder. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:525-526 [Conf]
  105. Y. Kuroda, J. Miyakoshi, M. Miyama, Kousuke Imamura, Hideo Hashimoto, M. Yoshimoto
    A sub-mW MPEG-4 motion estimation processor core for mobile video application. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:527-528 [Conf]
  106. Kimihiro Nishio, Hiroo Yonezu, Shinya Sawa, Yuzo Furukawa
    Analog LSI for motion detection of approaching object with simple-shape recognition based on lower animal vision. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:529-530 [Conf]
  107. Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
    350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:531-532 [Conf]
  108. Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo
    A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:533-534 [Conf]
  109. Simon C. Li, Vincent Chia-Chang Lin
    A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:535-536 [Conf]
  110. Naoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji Kotani, Tadahiro Ohmi
    A small-area high-performance 512-point 2-dimensional FFT single-chip processor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:537-538 [Conf]
  111. Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui
    Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:539-540 [Conf]
  112. Yoshihiro Utsurogi, Masaki Haruoka, Toshimasa Matsuoka, Kenji Taniguchi
    A dual-band image-reject mixer for GPS with 64dB image rejection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:541-542 [Conf]
  113. Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch
    Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:543-544 [Conf]
  114. Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera
    A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:545-546 [Conf]
  115. Yi-Ming Wang, Jinn-Shyan Wang
    A reliable low-power fast skew-compensation circuit. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:547-548 [Conf]
  116. Jun Ohta, Tetsuo Furumiya, David C. Ng, Akihiro Uehara, Keiichiro Kagawa, Takashi Tokuda, Masahiro Nunoshita
    A retinal prosthetic device using a pulse-frequency-modulation CMOS image sensor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:549-550 [Conf]
  117. Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka
    Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:551-552 [Conf]
  118. Chun-Pong Yu, Chiu-sing Choy, Hao Min, Cheong-fat Chan, Kong-Pang Pun
    A low power asynchronous Java processor for contactless smart card. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:553-554 [Conf]
  119. Keiichiro Kagawa, Tomoaki Kawakami, Hiroaki Asazu, Takashi Ikeuchi, Akiko Fujiuchi, Jun Ohta, Masahiro Nunoshita
    An image-sensor-based optical receiver fabricated in a standard 0.35-µm CMOS technology for free-space optical communications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:555-556 [Conf]
  120. Takeshi Ohkawa, Toshiyuki Nozawa, Masanori Fujibayashi, Naoto Miyamoto, Leo Karnan, Soichiro Kita, Koji Kotani, Tadahiro Ohmi
    The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:557-558 [Conf]
  121. Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui
    A dual--band switching digital controller for a buck converter. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:561-562 [Conf]
  122. Arunkumar Balasundaram, Angelo Pereira, Jun-Cheol Park, Vincent John Mooney III
    Golay and wavelet error control codes in VLSI. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:563-564 [Conf]
  123. Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang
    Timing measurement unit with multi-stage TVC for embedded memories. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:565-566 [Conf]
  124. J. Y. Yeom, T. Ishitsu, H. Takahashi
    Development of a waveform sampling front-end ASIC for PET. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:567-568 [Conf]
  125. Ryozo Katoh, Shin-ya Kobayashi, Takao Waho
    A dynamic element matching circuit for multi-bit delta-sigma modulators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:569-570 [Conf]
  126. Yoshihiro Iida, Naohiko Shimizu
    Design of POP-11 (PDP-11 on programmable chip). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:571-572 [Conf]
  127. Ekachai Leelarasmee, Kanitpong Pengwon
    A closed caption TV microcontroller. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:573-574 [Conf]
  128. Jun Ohta, Keiichiro Kagawa, Koichi Yamamoto, Takashi Tokuda, Yu Oya, Masahiro Nunoshita
    Improvement of saturation characteristics of a frequency-demodulation CMOS image sensor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:575-576 [Conf]
  129. Hala A. Farouk, Magdy Saeb
    Design and implementation of a secret key steganographic micro-architecture employing FPGA. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:577-578 [Conf]
  130. Maher N. Mneimneh, Karem A. Sakallah, John Moondanos
    Preserving synchronizing sequences of sequential circuits after retiming. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:579-584 [Conf]
  131. Tsutomu Sasao, Jon T. Butler
    A fast method to derive minimum SOPs for decomposable functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:585-590 [Conf]
  132. Debatosh Debnath, Tsutomu Sasao
    Efficient computation of canonical form for Boolean matching in large libraries. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:591-596 [Conf]
  133. Andrés Martinelli, René Krenz, Elena Dubrova
    Disjoint-support Boolean decomposition combining functional and structural methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:597-599 [Conf]
  134. Katsunori Tanaka, Yahiko Kambayashi
    Transduction method for design of logic cell structure. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:600-603 [Conf]
  135. Naoki Tokitsu
    The integration of vehicles into a ubiquitous computing environment computing and networking technologies for vehicles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:604-608 [Conf]
  136. Weiping Shi, Zhuo Li, Charles J. Alpert
    Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:609-614 [Conf]
  137. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    A buffer planning algorithm with congestion optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:615-620 [Conf]
  138. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Buffer allocation algorithm with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:621-623 [Conf]
  139. Yi-Hui Cheng, Yao-Wen Chang
    Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:624-627 [Conf]
  140. Robert Clarisó, Jordi Cortadella
    Verification of timed circuits with symbolic delays. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:628-633 [Conf]
  141. Tao Feng, Li-C. Wang, Kwang-Ting Cheng
    Improved symbolic simulation by functional-space decomposition. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:634-639 [Conf]
  142. Görschwin Fey, Rolf Drechsler
    Improving simulation-based verification by means of formal methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:640-643 [Conf]
  143. Tun Li, Yang Guo, Sikun Li, Fujiang Ao, GongJie Li
    Parallel verilog simulation: architecture and circuit partition. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:644-646 [Conf]
  144. Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
    Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:647-652 [Conf]
  145. Dongkun Shin, Jihong Kim
    Dynamic voltage scaling of periodic and aperiodic tasks in priority-driven systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:653-658 [Conf]
  146. Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David Jensen
    Fast and efficient voltage scheduling by evolutionary slack distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:659-662 [Conf]
  147. Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
    Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:663-665 [Conf]
  148. Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang
    A fast congestion estimator for routing with bounded detours. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:666-670 [Conf]
  149. Zion Cien Shen, Chris C. N. Chu
    Accurate and efficient flow based congestion estimation in floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:671-676 [Conf]
  150. Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu
    A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:677-682 [Conf]
  151. Jin-Tai Yan, Shun-Hua Lin
    Timing-constrained congestion-driven global routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:683-686 [Conf]
  152. Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
    Efficient octilinear Steiner tree construction based on spanning graphs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:687-690 [Conf]
  153. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
    Representative frequency for interconnect R(f)L(f)C extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:691-696 [Conf]
  154. Tao Jiang, Eric Pettus, Daksh Lehther
    A mixed-mode extraction flow for high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:697-701 [Conf]
  155. Liu Yang, Xiaobo Guo, Zeyi Wang
    An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:702-706 [Conf]
  156. Xiren Wang, Deyan Liu, Wenjian Yu, Zeyi Wang
    Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:707-709 [Conf]
  157. Rouying Zhan, Haigang Feng, Qiong Wu, Xiaokang Guan, Guang Chen, Haolu Xie, Albert Z. Wang
    Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:710-712 [Conf]
  158. Jason Helge Anderson, Farid N. Najm
    Interconnect capacitance estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:713-718 [Conf]
  159. Chi-Chou Kao, Yen-Tai Lai
    Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:719-724 [Conf]
  160. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen
    Temporal floorplanning using 3D-subTCG. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:725-730 [Conf]
  161. Yasunori Osana, Tomonori Fukushima, Hideharu Amano
    ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:731-733 [Conf]
  162. Young-Il Kim, Bong-Il Park, Jae-Gon Lee, Chong-Min Kyung
    SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:734-736 [Conf]
  163. Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
    An SoC architecture and its design methodology using unifunctional heterogeneous processor array. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:737-742 [Conf]
  164. Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
    Instruction set and functional unit synthesis for SIMD processor cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:743-750 [Conf]
  165. Ruibing Lu, Cheng-Kok Koh
    A high performance bus communication architecture through bus splitting. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:751-755 [Conf]
  166. Dongwan Shin, Samar Abdi, Daniel Gajski
    Automatic generation of bus functional models from transaction level models. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:756-758 [Conf]
  167. Hua Wang, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor
    A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:759-761 [Conf]
  168. Shuji Tsukiyama
    Toward stochastic design for digital circuits: statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:762-767 [Conf]
  169. Louis Scheffer
    Physical CAD changes to incorporate design for lithography and manufacturability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:768-773 [Conf]
  170. Guoyong Shi, C.-J. Richard Shi
    Parametric reduced order modeling for interconnect analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:774-779 [Conf]
  171. Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang
    Realizable parasitic reduction for distributed interconnects using matrix pencil technique. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:780-785 [Conf]
  172. Hao Ji, Qingjian Yu, Wayne Wei-Ming Dai
    SPICE compatible circuit models for partial reluctance K. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:786-791 [Conf]
  173. Clement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen
    Frequency-dependent reluctance extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:792-797 [Conf]
  174. Masahiko Kawamura, Hideharu Amano
    Future reconfigurable computing system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:798- [Conf]
  175. Tudor Dumitras, Sam Kerner, Radu Marculescu
    Enabling on-chip diversity through architectural communication design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:799-805 [Conf]
  176. Young-Su Kwon, Jae-Gon Lee, Chong-Min Kyung
    Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:806-811 [Conf]
  177. Lukai Cai, Haobo Yu, Daniel Gajski
    A novel memory size model for variable-mapping in system level design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:812-817 [Conf]
  178. Hojun Shim, Naehyuck Chang, Massoud Pedram
    A compressed frame buffer to reduce display power consumption in mobile systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:818-823 [Conf]
  179. Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal
    Instruction buffering exploration for low energy VLIWs with instruction clusters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:824-829 [Conf]
  180. Hidenori Sato, Toshinori Sato
    A static and dynamic energy reduction technique for I-cache and BTB in embedded processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:830-833 [Conf]
  181. Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
    Resource-constrained low-power bus encoding with crosstalk delay elimination. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:834-837 [Conf]
  182. Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis, Rainer Leupers
    Compiler based exploration of DSP energy savings by SIMD operations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:838-841 [Conf]
  183. Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Synthesizable HDL generation method for configurable VLIW processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:842-845 [Conf]
  184. Janet Meiling Wang, Omar Hafiz, Pinhong Chen
    A non-iterative model for switching window computation with crosstalk noise. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:846-851 [Conf]
  185. Soroush Abbaspour, Massoud Pedram
    Gate delay calculation considering the crosstalk capacitances. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:852-857 [Conf]
  186. Kanak Agarwal, Dennis Sylvester, David Blaauw
    A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:858-864 [Conf]
  187. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Minimization of the expected path length in BDDs based on local changes. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:865-870 [Conf]
  188. Shinobu Nagayama, Tsutomu Sasao
    Minimization of memory size for heterogeneous MDDs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:871-874 [Conf]
  189. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Combining ordered best-first search with branch and bound for exact BDD minimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:875-878 [Conf]
  190. Ruiming Li, Dian Zhou, Donglei Du
    Satisfiability and integer programming as complementary tools. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:879-882 [Conf]
  191. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    ShatterPB: symmetry-breaking for pseudo-Boolean formulas. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:883-886 [Conf]
  192. Fang Fang, Jianwen Zhu
    Automatic process migration of datapath hard IP libraries. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:887-892 [Conf]
  193. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:893-898 [Conf]
  194. Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy
    High-level area and power-up current estimation considering rich cell library. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:899-904 [Conf]
NOTICE1
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NOTICE2
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