Conferences in DBLP
Kimikazu Sano , Koichi Narahara , Koichi Murata , Taiichi Otsuji , Kiyomitsu Onodera High-speed GaAs MESFET Digital IC Design for Optical Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuya Yamamoto , Takao Moriwaki , Yutaka Yoshii , Takayuki Fujii , Jun Otsuji , Yoshinobu Sasaki , Yukio Miyazaki , Kazuo Nishitani Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R-MMIC Front-End for 1.9-GHz Personal Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Simon Cimin Li , Reggie Chien , Jerry Chien , Kaung-Long Lin A Simple Architecture of Low Voltage GHz BiCMOS Four-Quadrant Analogue Multiplier using Complementary Voltage Follower. [Citation Graph (0, 0)][DBLP ] Conf ] Sri Parameswaran HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Becker , Reiner W. Hartenstein , Michael Herz , Ulrich Nageldinger Parallelization in Co-Compilation for Configurable Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Kawaguchi , Takayasu Sakurai Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Pandini , Primo Scandolara , Carlo Guardiani Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Shuji Takahashi , Masato Edahiro , Yoshihiro Hayashi A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Yamashita , Hiroshi Sawada , Akira Nagoya New Methods to Find Optimal Non-Disjoint Bi-Decompositions. [Citation Graph (0, 0)][DBLP ] Conf ] Debatosh Debnath , Tsutomu Sasao A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Gueesang Lee , Rolf Drechsler ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Meinel , Fabio Somenzi , Thorsten Theobald Function Decomposition and Synthesis Using Linear Sifting. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Leupers , Anupam Basu , Peter Marwedel Optimized Array Index Computation in DSP Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Yamaguchi , Nagisa Ishiura , Takashi Kambe Binding and Scheduling Algorithms for Highly Retargetable Compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Guo , Sri Parameswaran Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Chunho Lee , Miodrag Potkonjak Quantitative Selection of Media Benchmarks. [Citation Graph (0, 0)][DBLP ] Conf ] Morikazu Tsuno , Masato Suga , Masayasu Tanaka , Kentaro Shibahara , Michiko Miura-Mattausch , Masataka Hirose Reliable Threshold Voltage Determination for Sub-0.1µm Gate Length MOSFET's. [Citation Graph (0, 0)][DBLP ] Conf ] Seiichiro Yamaguchi , Hiroshi Goto Inverse Modeling - A Promising Approach to Know What Is Made and What Should Be Made. [Citation Graph (0, 0)][DBLP ] Conf ] Ute Feldmann , R. Kakoschke , Michiko Miura-Mattausch , G. Schraud Concurrent Technology, Device, and Circuit Development for EEPROMs. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroo Masuda , Katsumi Tsuneno , Hisako Sato , Kazutaka Mori TCAD/DA for MPU and ASIC Development. [Citation Graph (0, 0)][DBLP ] Conf ] Massoud Pedram Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Gee Chen , Juing-Ying Jiu , Hao-Chieh Chang , Yung-Pin Lee , Chung-Wei Ku A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , Amit Sinha , Sunil D. Sherlekar Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Sung Hyun Yoon , Myung Hoon Sunwoo An Efficient Variable-Length Tap FIR Filter Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Kaoru Suzuki , Shunsuke Miyamoto , Masato Kurosaki , Junji Nakagoshi Effective Simulation for the Giga-scale Massively Parallel Supercomputer SR2201. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuhiro Yasuda , Katsuhiko Seo , Hisao Koizumi , Barry Shackleford , Fumio Suzuki A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Wonyong Sung , Soonhoi Ha A Hardware Software Cosimulation Backplane with Automatic Interface Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Mohit Sahni , Takashi Nanya On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Uisok Kim , Dong-Ik Lee Practical Synthesis of Speed-Independent Circuits Using Unfoldings. [Citation Graph (0, 0)][DBLP ] Conf ] Kouji Takano , Takehito Sasaki , Nobuyuki Oba , Hiroaki Kobayashi , Tadao Nakamura Automated Design of Wave Pipelined Multiport Register Files. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Anand Raghunathan , Rabindra K. Roy Considering Testability during High-level Design (Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Tomoya Takasaki , Tomoo Inoue , Hideo Fujiwara Partial Scan Design Methods Based on Internally Balanced Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita Model Checking: Its Basics and Reality (Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Kazuo Taki A Survey for Pass-Transistor Logic Technologies - Recent Researches and Developments and Future Prospects (Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh R. Bettadapur Software Licensing Models in the EDA Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Hisakazu Edamatsu , Katsumi Homma , Masaru Kakimoto , Yutaka Koike , Kinya Tabuchi Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Cottrell , David Mallis , Joseph Morrell CHDStd - A Model for Deep Submicron Design Tools. [Citation Graph (0, 0)][DBLP ] Conf ] S. Grout , G. Ledenbach , R. G. Bushroe , P. Fisher , D. Cottrell , D. Mallis , S. DasGupta , J. Morrell , J. Sayah , R. Gupta , P. T. Patel , P. Adams Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Allara , Massimo Bombana , Patrizia Cavalloro , Wolfgang Nebel , Wolfram Putzke-Röming , Martin Radetzki ATM Cell Modelling using Objective VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Nozomu Togawa , Takafumi Hisaki , Masao Yanagisawa , Tatsuo Ohtsuki A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Tomiyama , Hiroto Yasuura Module Selection Using Manufacturing Information. [Citation Graph (0, 0)][DBLP ] Conf ] Inki Hong , Miodrag Potkonjak Techniques for Functional Test Pattern Execution. [Citation Graph (0, 0)][DBLP ] Conf ] Inki Hong , Miodrag Potkonjak , Ramesh Karri Heterogeneous BISR-approach using System Level Synthesis Flexibility. [Citation Graph (0, 0)][DBLP ] Conf ] Jinan Lou , Amir H. Salek , Massoud Pedram An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Susumu Kobayashi , Masato Edahiro , Mikio Kubo Scan-chain Optimization Algorithms for Multiple Scan-paths. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Kitahara , Fumihiro Minami , Toshiaki Ueda , Kimiyoshi Usami , Seiichi Nishio , Masami Murakata , Takashi Mitsuhashi A Clock-Gating Method for Low-Power LSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jaewon Oh , Massoud Pedram Power Reduction in Microprocessor Chips by Gated Clock Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Akihiro Takamura , Motokazu Ozawa , Izumi Fukasaku , Taro Fujii , Yoichiro Ueno , Masashi Imai , Masashi Kuwako , Takashi Nanya TITAC-2: An Asynchronous 32-bit Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Tohru Ishihara , Hiroto Yasuura Power-Pro: Programmable Power Management Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Komatsu , Makoto Ikeda , Kunihiro Asada Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Hyuk Yang , Byung-Woon Kim , Sung-Won Seo , Sang-Jun Nam , Chang-Ho Ryu , Jang-Ho Cho , Chong-Min Kyung Metacore: A Configurable and Instruction Level Extensible DSP Core. [Citation Graph (0, 0)][DBLP ] Conf ] Ho Keun Jang A Design of Sound Synthesis IC. [Citation Graph (0, 0)][DBLP ] Conf ] Se Young Eun , Myung Hoon Sunwoo An Effcient 2-D Convolver Chip for Real Time Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Isshiki , Takenobu Shimizugashira , Akihisa Ohta , Imanuddin Amril , Hiroaki Kunieda FPGA for High-Performance Bit-Serial Pipeline Datapath. [Citation Graph (0, 0)][DBLP ] Conf ] K. Hirano , T. Ono , Hiroyuki Kurino , Mitsumasa Koyanagi A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. [Citation Graph (0, 0)][DBLP ] Conf ] M. Bickerstaff , T. Arivoli , Philip J. Ryan , Neil Weste , David J. Skellern A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Midorikawa , Takayuki Kamei , Toshihiro Hanawa , Hideharu Amano The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Shoji Kawahito , Makoto Yoshida , Masaaki Sasaki , Daisuke Miyazaki , Yoshiaki Tadokoro , Kenji Murata , Shiro Doushou , Akira Matsuzawa A CMOS Smart Image Sensor LSI for Focal-Plane Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Changsik Yoo , Wonchan Kim A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Hamamoto , Kiyoharu Aizawa , Mitsutoshi Hatori Motion Adaptive Image Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan , Sandip Kundu Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Tae Hun Kim , Beomsup Kim Dual-loop Digital PLL Design for Adaptive Clock Recovery. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Henkel , Rolf Ernst High-Level Estimation Techniques for Usage in Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jinhwan Jeon , Kiyoung Choi Loop Pipelining in Hardware-Software Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Nguyen-Ngoc Bình , Masaharu Imai , Yoshinori Takeuchi A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. [Citation Graph (0, 0)][DBLP ] Conf ] Jiang-An He , Hideaki Kobayashi Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Wonjong Kim , Hyunchul Shin Hierarchical LVS Based on Hierarchy Rebuilding. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiyuki Hama , Hiroaki Etoh Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-Fattening. [Citation Graph (0, 0)][DBLP ] Conf ] Tim A. Schreyer Tool Capabilities Needed for Designing 100 MHz Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Tarui , Takehiro Takahashi , Noboru Schibuya Development of a Support Tool for PCB Design with EMC Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuhisa Mido , Kunihiro Asada An Analysis on VLSI Interconnection Considering Skin Effect. [Citation Graph (0, 0)][DBLP ] Conf ] X. Zeng , P. S. Tang , C. K. Tse Design of Nonlinear Switched-Current Circuits Using Building Block Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Tae-Min Kim , Gun Sun Shin A Circuit Design of 16x16 Multiplier Using Redundant Binary Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Massoud Pedram , Qing Wu , Xunwei Wu A New Design for Double Edge Triggered Flip-flops. [Citation Graph (0, 0)][DBLP ] Conf ] Bwolen Yang , Yirng-An Chen , Randal E. Bryant , David R. O'Hallaron Space- and Time-Efficient BDD Construction via Working Set Control. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Stefan Höreth Manipulation of *BMDs. [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic , Tsutomu Sasao Decision Diagrams for Discrete Functions: Classification and Unified Interpretation. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiaki Miyazaki Reconfigurable Systems: A Survey (Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Yuichiro Shibata Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Miyako Tandai , Takao Shinsha A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Debesh K. Das , Susanta Chakraborty , Bhargab B. Bhattacharya Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Reza Sedaghat-Maman , Erich Barke Real Time Fault Injection Using Logic Emulators. [Citation Graph (0, 0)][DBLP ] Conf ] João P. Marques Silva Integer Programming Models for Optimization Problems in Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Funaba , Akihiro Kitagawa , Toshiro Tsukada , Goichi Yokomizo A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Wolf , Ulrich Kleine , Frédéric Schafer A Novel Design Assistant for Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] C.-J. Richard Shi , Michael W. Tian Automatic Test Generation for Linear Analog Circuits under Parameter Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Reiji Suda , Yoshio Oyanagi The Ensparsed LU Decomposition Method for Large Scale Circuit Transient Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Rongzheng Zhou , Jiarong Tong , Pushan Tang FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Nozomu Togawa , Kayoko Hagi , Masao Yanagisawa , Tatsuo Ohtsuki An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Murooka , Atsushi Takahara , Toshiaki Miyazaki , Akihiro Tsutsui An Architecture-oriented Routing Method for FPGAs Having Rich Hierarchical Routing Resources. [Citation Graph (0, 0)][DBLP ] Conf ] Jiaofeng Pan , Yu-Liang Wu , C. K. Wong On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] C.-J. Richard Shi Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Sri Parameswaran , Hui Guo Power Reduction in Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Min Jiang , Shi-Yu Huang , Kwang-Ting Cheng , Deborah C. Wang , ChingYen Ho A Hybrid Power Model for RTL Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Darko Kirovski , Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith Synthesis of Power Efficient Systems-on-Silicon. [Citation Graph (0, 0)][DBLP ] Conf ] Tomonori Izumi , Atsushi Takahashi , Yoji Kajitani Air-Pressure-Model-Based Fast Algorithms for General Floorplan. [Citation Graph (0, 0)][DBLP ] Conf ] Shigetoshi Nakatake , Masahiro Furuya , Yoji Kajitani Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsushi Koide , Shin'ichi Wakabayashi A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Weste , David J. Skellern , Terry Percival VLSI for Multimedia U-NII WLANs. [Citation Graph (0, 0)][DBLP ] Conf ] Takao Onoye , Gen Fujita , Hiroyuki Okuhata , Morgan Hirosuke Miki , Isao Shirakawa Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Shoji Kawahito , Yoshiaki Tadokoro , Akira Matsuzawa CMOS Image Sensors with Video Compression. [Citation Graph (0, 0)][DBLP ] Conf ] 