Conferences in DBLP

SAMOS Workshops (samos)
2002 (conf/samos/2002)

1. Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
   Consistency Analysis of Reconfigurable Dataflow Specifications. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:1-17 [Conf]
   
2. Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
   A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:18-37 [Conf]
   
3. Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
   Flexibility/Cost-Tradeoffs of Platform-Based Systems. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:38-56 [Conf]
   
4. Andy D. Pimentel, Simon Polstra, Frank Terpstra, A. W. van Halderen, Joseph E. Coffland, Louis O. Hertzberger
   Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:57-73 [Conf]
   
5. Vladimir D. Zivkovic, Paul Lieverse
   An Overview of Methodologies and Tools in the Field of System-Level Design. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:74-88 [Conf]
   
6. Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis
   Translating Imperative Affine Nested Loop Programs into Process Networks. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:89-111 [Conf]
   
7. Patrice Quinton, Tanguy Risset
   Structured Scheduling of Recurrence Equations: Theory and Practice. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:112-134 [Conf]
   
8. Jürgen Teich, Lothar Thiele
   Exact Partitioning of Affine Dependence Algorithms. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:135-153 [Conf]
   
9. Marcus Bednara, Frank Hannig, Jürgen Teich
   Generation of Distributed Loop Control. [Citation Graph (0, 0)][DBLP]
   Embedded Processor Design Challenges, 2002, pp:154-170 [Conf]
   
10. Peter M. W. Knijnenburg, Toru Kisuki, Michael F. P. O'Boyle
    Iterative Compilation. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:171-187 [Conf]
    
11. Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg
    Processor Architectures for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:188-206 [Conf]
    
12. Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
    Microcoded Reconfigurable Embedded Processors: Current Developments. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:207-223 [Conf]
    
13. Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
    A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:224-241 [Conf]
    
14. Henk L. Muller, Dan Page, James Irwin, David May
    Caches with Compositional Performance. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:242-259 [Conf]
    
15. Clark N. Taylor, Debashis Panigrahi, Sujit Dey
    Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:260-273 [Conf]
    
16. Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest
    Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:274-290 [Conf]
    
17. Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven
    A 2D Addressing Mode for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:291-306 [Conf]
    
18. C. John Glossner, Michael J. Schulte, Stamatis Vassiliadis
    A Java-Enabled DSP. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:307-326 [Conf]