Conferences in DBLP
Stamatis Vassiliadis , Georgi Gaydadjiev , Koen Bertels , Elena Moscu Panainte The Molen Programming Paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Georgi Kuzmanov , Georgi Gaydadjiev , Stamatis Vassiliadis Loading rho-µ-Code: Design Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Stéphane Chevobbe , Nicolas Ventroux , Frédéric Blanc , Thierry Collette RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Haubelt , Dirk Koch , Jürgen Teich Basic OS Support for Distributed Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Peter Wittenburg , Ulrich Schreiber , Ulrich Gries , Markus Schneider 0003 , Tim Niggemeier A Cost-Efficient RISC Processor Platform for Real Time Audio Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Luk Customising Processors: Design-Time and Run-Time Opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Erwan Fabiani , Christophe Gouyen , Bernard Pottier Intermediate Level Components for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten Reuter , Javier Martín-Langerwerf , Hans-Joachim Stolberg , Peter Pirsch Performance Estimation of Streaming Media Applications for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Radhakrishnan Sivakumar , Vassilios V. Dimakopoulos , Nikitas J. Dimopoulos CoDeL: Automatically Synthesizing Network Interface Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Miquel Pericàs , Eduard Ayguadé , Javier Zalamea , Josep Llosa , Mateo Valero with Wide Functional Units. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Heinkel , Claus Mayer , Charles F. Webb , Hans Sahm , Werner Haas , Stefan Gossens An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Tuomas Järvinen , Jarmo Takala Register-Based Permutation Networks for Stride Permutations. [Citation Graph (0, 0)][DBLP ] Conf ] David Guevorkian , Petri Liuha , Aki Launiainen , Ville Lappalainen A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Benoit , Gilles Sassatelli , Lionel Torres , Didier Demigny , Michel Robert , Gaston Cambon Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Kogel , Malte Doerper , Torsten Kempf , Andreas Wieferink , Rainer Leupers , Gerd Ascheid , Heinrich Meyr Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Miia Viitanen , Timo D. Hämäläinen Comparison of Data Dependence Analysis Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon Cichon , Gerhard Fettweis MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Crisu , Sorin Cotofana , Stamatis Vassiliadis , Petri Liuha High-Level Energy Estimation for ARM-Based SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Cagkan Erbas , Simon Polstra , Andy D. Pimentel IDF Models for Trace Transformations: A Case Study in Computational Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Kees A. Vissers Programming Extremely Flexible Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Georgi Kuzmanov , Georgi Gaydadjiev , Stamatis Vassiliadis The Virtex II ProTM MOLEN Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Stroobandt , Hendrik Eeckhaut , Harald Devos , Mark Christiaens , Fabio Verdicchio , Peter Schelkens Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro C. Diniz Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] João M. P. Cardoso , Pedro C. Diniz Modeling Loop Unrolling: Approaches and Open Issues. [Citation Graph (0, 0)][DBLP ] Conf ] João M. P. Cardoso Self-loop Pipelining and Reconfigurable Dataflow Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] François Charot , Madeleine Nyamsi , Patrice Quinton , Charles Wagner Architecture Exploration for 3G Telephony Applications Using a Hardware-Software Prototyping Platform. [Citation Graph (0, 0)][DBLP ] Conf ] John McAllister , Roger Woods , Richard Walke Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Jérôme Lemaitre , Sylvain Alliot , Ed F. Deprettere On the (Re-)Use of IP-Components in Re-configurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Telle , Wayne Luk , Ray C. C. Cheung Customising Hardware Designs for Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Moscu Panainte , Koen Bertels , Stamatis Vassiliadis Dynamic Hardware Reconfigurations: Performance Impact for MPEG2. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Cambonie , Sylvain Guérin , Ronan Keryell , Loïc Lagadec , Bernard Pottier , Olivier Sentieys , Bernt Weber , Samar Yazdani Compiler and System Techniques for soc Distributed Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Júlio C. B. de Mattos , Antonio Carlos Schneider Beck , Luigi Carro , Flávio Rech Wagner Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Hosemann , Gerhard Fettweis On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Iosif Antochi , Ben H. H. Juurlink , Stamatis Vassiliadis , Petri Liuha Memory Bandwidth Requirements of Tile-Based Rendering. [Citation Graph (0, 0)][DBLP ] Conf ] Nainesh Agarwal , Nikitas J. Dimopoulos Using CoDeL to Rapidly Prototype Network Processsor Extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon Cichon , Pablo Robelly , Hendrik Seidel , Emil Matús , Marcus Bronzel , Gerhard Fettweis Synchronous Transfer Architecture (STA). [Citation Graph (0, 0)][DBLP ] Conf ] Hendrik Seidel , Emil Matús , Gordon Cichon , Pablo Robelly , Marcus Bronzel , Gerhard Fettweis Generated DSP Cores for Implementation of an OFDM Communication System. [Citation Graph (0, 0)][DBLP ] Conf ] Michalis D. Galanis , George Theodoridis , Spyros Tragoudas , Dimitrios Soudris , Costas E. Goutis A Novel Data-Path for Accelerating DSP Kernels. [Citation Graph (0, 0)][DBLP ] Conf ] Jarmo Takala , Konsta Punkka Scalable FFT Processors and Pipelined Butterfly Units. [Citation Graph (0, 0)][DBLP ] Conf ] Chris R. Jesshope Scalable Instruction-Level Parallelism.. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Schulte , C. John Glossner , Suman Mamidi , Mayan Moudgill , Stamatis Vassiliadis A Low-Power Multithreaded Processor for Baseband Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Esther Salamí , Mateo Valero Initial Evaluation of Multimedia Extensions on VLIW Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Erno Salminen , Vesa Lahtinen , Tero Kangas , Jouni Riihimäki , Kimmo Kuusilinna , Timo D. Hämäläinen HIBI v.2 Communication Network for System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Jui Hsu , Fuat Keceli , Ming-Yung Ko , Shahrooz Shahparnia , Shuvra S. Bhattacharyya DIF: An Interchange Format for Dataflow-Based Design Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Feautrier Scalable and Modular Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Wieferink , Malte Doerper , Tim Kogel , Rainer Leupers , Gerd Ascheid , Heinrich Meyr Early ISS Integration into Network-on-Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Antoine Fraboulet , Tanguy Risset , Antoine Scherrer Cycle Accurate Simulation Model Generation for SoC Prototyping. [Citation Graph (0, 0)][DBLP ] Conf ] Jianjiang Ceng , Weihua Sheng , Manuel Hohenauer , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Gunnar Braun Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP ] Conf ] Tero Kangas , Jouni Riihimäki , Erno Salminen , Vesa Lahtinen , Heikki Orsila , Kimmo Kuusilinna , Timo D. Hämäläinen A Communication-Centric Design Flow for HIBI-Based SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Blume , Thorsten von Sydow , Tobias G. Noll Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Ioan Cimpian , Alexandru Turjan , Ed F. Deprettere , Erwin A. de Kock Communication Optimization in Compaan Process Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Teich , Shuvra S. Bhattacharyya Analysis of Dataflow Programs with Interval-Limited Data-Rates. [Citation Graph (0, 0)][DBLP ] Conf ] Alexey Kupriyanov , Frank Hannig , Jürgen Teich High-Speed Event-Driven RTL Compiled Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Thompson , Andy D. Pimentel A High-Level Programming Paradigm for SystemC. [Citation Graph (0, 0)][DBLP ] Conf ] Minas Dasygenis , Erik Brockmeyer , Bart Durinck , Francky Catthoor , Dimitrios Soudris , Antonios Thanailakis Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Laurentiu Nicolae , Ed F. Deprettere Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] 