Conferences in DBLP
Robert A. Iannucci Platform Thinking in Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Moscu Panainte , Koen Bertels , Stamatis Vassiliadis Interprocedural Optimization for Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Glesner , Heiko Hinkelmann , Thomas Hollstein , Leandro Soares Indrusiak , Tudor Murgan , Abdulfattah Mohammad Obeid , Mihail Petrov , Thilo Pionteck , Peter Zipf Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Humberto Calderon , Stamatis Vassiliadis Reconfigurable Multiple Operation Array. [Citation Graph (0, 0)][DBLP ] Conf ] Guillermo Payá Vayá , Javier Martín-Langerwerf , Peter Pirsch RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Ferreira , João M. P. Cardoso , Andre Toledo , Horácio C. Neto Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Ruckdeschel , Hritam Dutta , Frank Hannig , Jürgen Teich Automatic FIR Filter Generation for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Pablo Robelly , A. Lehmann , Gerhard Fettweis Two-Dimensional Fast Cosine Transform for Vector-STA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Guy Gogniat , Wayne Burleson , Lilian Bossuet Configurable Computing for High-Security/High-Performance Ambient Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai-Lucian Cristea , Claudiu Zissulescu , Ed F. Deprettere , Herbert Bos FPL-3E: Towards Language Support for Reconfigurable Packet Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Georgi Gaydadjiev , Stamatis Vassiliadis Flux Caches: What Are They and Are They Useful? [Citation Graph (0, 0)][DBLP ] Conf ] Cheol Hong Kim , Sung-Hoon Shim , Jong Wook Kwak , Sung Woo Chung , Chu Shik Jhon First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Yiyu Tan , Chihang Yau , Kaiman Lo , Pak Lun Mok , Anthony S. Fong A Novel JAVA Processor for Embedded Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Tomi Westerlund , Juha Plosila Formal Specification of a Protocol Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Jani Paakkulainen , Seppo Virtanen , Jouni Isoaho Tuning a Protocol Processor Architecture Towards DSP Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Olli Silvén , Kari Jyrkkä Observations on Power-Efficiency Trends in Mobile Communication Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Sima , John Glossner , Daniel Iancu , Hua Ye , Andrei Iancu , A. Joseph Hoane CORDIC-Augmented Sandbridge Processor for Channel Equalization. [Citation Graph (0, 0)][DBLP ] Conf ] Sunghoon Shim , Jong Wook Kwak , Cheol Hong Kim , Sung Tae Jhang , Chu Shik Jhon Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Gao , Suleyman Sair Exploiting Intra-function Correlation with the Global History Stack. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh C. Suresh , Walid A. Najjar , Jun Yang Power Efficient Instruction Caches for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Lucanus Simonson , Lei He Micro-architecture Performance Estimation by Formula. [Citation Graph (0, 0)][DBLP ] Conf ] Frederik Vandeputte , Lieven Eeckhout , Koen De Bosschere Offline Phase Analysis and Optimization for Multi-configuration Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Teemu Pitkänen , Tommi Rantanen , Andrea G. M. Cilio , Jarmo Takala Hardware Cost Estimation for Application-Specific Processor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Farfeleder , Andreas Krall , R. Nigel Horspool Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Marcel Beemster , Hans van Someren , Liam Fitzpatrick , Ruben van Royen Generating Stream Based Code from Plain C. [Citation Graph (0, 0)][DBLP ] Conf ] Sangchul Han , Moonju Park , Yookun Cho Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Zhang , Zeng-zhi Li , Hong Song , Long Liu A Programming Model for an Embedded Media Processing Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Leonardo Taglietti , José O. Carlomagno Filho , Daniel C. Casarotto , Olinto J. V. Furtado , Luiz C. V. dos Santos Automatic ADL-Based Assembler Generation for ASIP Programming Support. [Citation Graph (0, 0)][DBLP ] Conf ] C. John Glossner , Sean Dorward , Sanjay Jinturkar , Mayan Moudgill , Erdem Hokenek , Michael J. Schulte , Stamatis Vassiliadis Sandbridge Software Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Marchand , Purnendu Sinha A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil Kim Pattern Matching Acceleration for Network Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sunghwan Lee , JongSu Yi , JunSeong Kim Real-Time Stereo Vision on a Reconfigurable System. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Manzak , Hüseyin Göksu Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sangduck Park , Hyunjin Lim , Hoseok Chang , Wonyong Sung Compressed Swapping for NAND Flash Memory Based Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Guevorkian , Petri Liuha , Aki Launiainen , Konsta Punkka , Ville Lappalainen A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Chunhui Zhang , Yun Long , Fadi J. Kurdahi A Scalable Embedded JPEG2000 Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Hu , Tong Jing , Xianlong Hong , Xiaodong Hu , Guiying Yan A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. [Citation Graph (0, 0)][DBLP ] Conf ] Erno Salminen , Tero Kangas , Jouni Riihimäki , Vesa Lahtinen , Kimmo Kuusilinna , Timo D. Hämäläinen Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context. [Citation Graph (0, 0)][DBLP ] Conf ] Kyriakos Stavrou , Paraskevas Evripidou , Pedro Trancoso DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Blume , Thorsten von Sydow , Daniel Becker , Tobias G. Noll Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Mauri Kuorilehto , Mikko Kohvakka , Marko Hännikäinen , Timo D. Hämäläinen High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Maziar Goudarzi , Shaahin Hessabi The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models. [Citation Graph (0, 0)][DBLP ] Conf ] Petri Kukkala , Marko Hännikäinen , Timo D. Hämäläinen Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] John McAllister , Roger Woods , D. Reilly , S. Fischaber , R. Hasson Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Bomel , Nabil Abdelli , Eric Martin , A.-M. Fouilliart , Emmanuel Boutillon , Philippe Kajfasz DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. [Citation Graph (0, 0)][DBLP ] Conf ] Sören Sonntag , Matthias Gries , Christian Sauer SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC. [Citation Graph (0, 0)][DBLP ] Conf ] Marijn Temmerman , Edgar G. Daylight , Francky Catthoor , Serge Demeyer , Tom Dhaene Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Andy D. Pimentel A Case for Visualization-Integrated System-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Eilers , Christian Müller-Schloer s Mixed Virtual/Real Prototypes for Incremental System Design - A Proof of Concept. [Citation Graph (0, 0)][DBLP ] Conf ] 