Conferences in DBLP

Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) (sbac-pad)
2002 (conf/sbac-pad/2002)

1. Ronald H. Perrott
   Infrastructure, Requirements and Applications for e-Science. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:3-12 [Conf]
   
2. Johann Großschädl
   Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:13-19 [Conf]
   
3. Manuel L. Anido, Nader Bagherzadeh, Nozar Tabrizi, Haitao Du, Marcos Sanchez-Elez
   Interactive Ray Tracing Using a SIMD Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:20-28 [Conf]
   
4. Dênis Fernandes, J. Stedile, Philippe Olivier Alexandre Navaux
   Architecture of Oscillatory Neural Network for Image Segmentation. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:29-38 [Conf]
   
5. G. Sipahi, G. Travieso
   Simulating Semiconductor Spectra Emissions in a PC Cluster. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:39-43 [Conf]
   
6. R. Silva, M. Rivello, R. Amorim
   Improving the Communication Network of a Cluster of PC's to Solve Implicit CFD Problems. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:44-50 [Conf]
   
7. Manoel T. F. Cunha, J. C. F. Telles, Alvaro L. G. A. Coutinho
   Parallel Boundary Elements Using Lapack and ScaLapack. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:51-60 [Conf]
   
8. Rafael Dueire Lins
   Efficient Cyclic Weighted Reference Counting. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:61-67 [Conf]
   
9. R. Guimarães, W. da Cunha Borelli
   Generating Java Code for TINA Systems. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2002, pp:68-74 [Conf]
   
10. D. Ruchkys, S. Song
    A Parallel Approximation Hitting Set Algorithm for Gene Expression Analysis. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:75-81 [Conf]
    
11. André Rauber Du Bois, Robert F. Pointon, Hans-Wolfgang Loidl, Philip W. Trinder
    Implementing Declarative Parallel Bottom-Avoiding Choice. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:82-92 [Conf]
    
12. Jin-Hyuck Choi, Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
    An Advanced Filtering TLB for Low Power Consumption. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:93-99 [Conf]
    
13. A. Djordjalian
    Minimally-Skewed-Associative Caches. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:100-107 [Conf]
    
14. M. Watson, J. Flanagan
    Simulating L3 Caches in Real Time Using Hardware Accelerated Cache Simulation (HACS): A Case Study with SPECint 2000. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:108-116 [Conf]
    
15. Leonardo Bidese de Pinho, Claudio Luis de Amorim, Edison Ishikawa
    GloVE: A Distributed Environment for Low Cost Scalable VoD Systems. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:117-124 [Conf]
    
16. Adenauer C. Yamin, Jorge L. V. Barbosa, Iara Augustin, Luciano Cavalheiro da Silva, Rodrigo Araujo Real, Cláudio F. R. Geyer, Gerson G. H. Cavalheiro
    A Framework for Exploiting Adaptation in Highly Heterogeneous Distributed Processing. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:125-132 [Conf]
    
17. Cristina Boeres, Vinod E. F. Rebello
    Cluster-Based Static Scheduling: Theory and Practice. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:133-140 [Conf]
    
18. César A. F. De Rose, Franco Blanco, Nicolas Maillard, Katia B. Saikoski, Reynaldo Novaes, O. Richard, Bruno Richard
    The Virtual Cluster: A Dynamic Environment for Exploitation of Idle Network Resources. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:141-150 [Conf]
    
19. E. Pineschi, Maria C. S. de Castro, Claudio Luis de Amorim
    Design and Evaluation of Data Access Prediction Strategies in SDSM Systems. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:151-158 [Conf]
    
20. T. Trevisan, Vítor Santos Costa, L. Whately, Claudio Luis de Amorim
    Distributed Shared Memory in Kernel Mode. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:159-168 [Conf]
    
21. Edil S. Tavares Fernandes, Valmir C. Barbosa, Fabiano Ramos
    Instruction Usage and the Memory Gap Problem. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:169-175 [Conf]
    
22. D. Becker, J. Otero, F. Wagner
    T&D-Bench: An Environment for Modeling and Simulating Complex Processor Architectures. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:176-183 [Conf]
    
23. C. Lima, T. Nakamura
    Exploiting Loop-Level Parallelism with the Shift Architecture. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:184-194 [Conf]
    
24. Anca I. D. Bucur, Dick H. J. Epema
    An Evaluation of Processor Co-allocation for Different System Configurations and Job Structures. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:195-203 [Conf]
    
25. Luís Fabrício Wanderley Góes, Luiz Eduardo da Silva Ramos, Carlos Augusto Paiva da Silva Martins
    Performance Analysis of Parallel Programs Using Prober as a Single Aid Tool. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:204-211 [Conf]
    
26. Jenny Yan Liu
    Performance and Scalability Measurement of COTS EJB Technology. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:212-220 [Conf]