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Conferences in DBLP

(sbcci)
2004 (conf/sbcci/2004)

  1. Enrico Macii
    RTL power estimation and optimization. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:1- [Conf]
  2. Chandu Visweswariah
    Statistical analysis and design: from picoseconds to probabilities. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:2- [Conf]
  3. Mike Hutton
    Architecture and CAD for FPGAs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:3- [Conf]
  4. José Luis Huertas
    Test and design-for-test of mixed-signal integrated circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:4- [Conf]
  5. Raul Camposano
    Will the ASIC survive? [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:5- [Conf]
  6. Armando Carbonari
    Avionic systems overview. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:6- [Conf]
  7. Enrico Macii
    Leakage power optimization in standard-cell designs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:7- [Conf]
  8. Mike Hutton
    Advances and trends in FPGA design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:8- [Conf]
  9. César Augusto Dueñas M.
    Verification and test challenges in SoC designs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:9- [Conf]
  10. Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes
    PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:10-15 [Conf]
  11. Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusebio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino S. Filho
    A partial reconfigurable architecture for controllers based on Petri nets. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:16-21 [Conf]
  12. Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich
    Task scheduling for heterogeneous reconfigurable computers. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:22-27 [Conf]
  13. Michael Hübner, Tobias Becker, Jürgen Becker
    Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:28-32 [Conf]
  14. Hamilton Klimach, Alfredo Arnaud, Márcio C. Schneider, Carlos Galup-Montoro
    Characterization of MOS transistor current mismatch. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:33-38 [Conf]
  15. Antonio Petraglia, Jorge M. Cañive, Mariane R. Petraglia
    A 0.8 mum CMOS switched-capacitor video filter. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:39-43 [Conf]
  16. Andre Vilas Boas, J. B. D. Soldera, Alfredo Olmos
    A 1.8V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:44-48 [Conf]
  17. Eric E. Fabris, Luigi Carro, Sergio Bampi
    Modeling and designing high performance analog reconfigurable circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:49-54 [Conf]
  18. Fernando Cortez Sica, Claudionor José Nunes Coelho Jr., José Augusto Miranda Nacif, Harry Foster, Antônio Otávio Fernandes
    Exception handling in microprocessors using assertion libraries. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:55-59 [Conf]
  19. Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione
    TheoSim: combining symbolic simulation and theorem proving for hardware verification. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:60-65 [Conf]
  20. Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta
    An automatic testbench generation tool for a SystemC functional verification methodology. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:66-70 [Conf]
  21. Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante
    A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:71-75 [Conf]
  22. José Vieira do Vale Neto
    Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:76-81 [Conf]
  23. Virgínia Helena Varotto Baroncini, Oscar da Costa Gouveia-Filho
    Design of RF CMOS low noise amplifiers using a current based MOSFET model. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:82-87 [Conf]
  24. C. P. Moreira, Eric Kerherve, P. Jarry, A. A. Shirakawa, Didier Belot
    Dual-mode RF receiver front-end using a 0.25-µm 60-GHz fTSiGe: C BiCMOS7RF technology. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:88-93 [Conf]
  25. Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
    A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:94-99 [Conf]
  26. Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho
    ATPG for fault diagnosis on analog electrical networks using evolutionary techniques. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:100-104 [Conf]
  27. Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski
    Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:105-110 [Conf]
  28. Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes
    Reducing test time with processor reuse in network-on-chip based systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:111-116 [Conf]
  29. Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Accurate capture of timing parameters in inductively-coupled on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:117-122 [Conf]
  30. João M. S. Silva, L. Miguel Silveira
    Issues in parallelizing multigrid-based substrate model extraction and analysis. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:123-128 [Conf]
  31. Gabriella Trucco, Giorgio Boselli, Valentino Liberali
    An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:129-134 [Conf]
  32. Klaus Danne
    Distributed arithmetic FPGA design with online scalable size and performance. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:135-140 [Conf]
  33. Alexander Thomas, Thomas Zander, Jürgen Becker
    Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:141-146 [Conf]
  34. Edgar Mauricio Camacho-Galeano, Carlos Galup-Montoro, Márcio C. Schneider
    An ultra-low-power self-biased current reference. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:147-150 [Conf]
  35. Alfredo Arnaud, Carlos Galup-Montoro
    A fully integrated physical activity sensing circuit for implantable pacemakers. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:151-156 [Conf]
  36. Antonio Carlos Schneider Beck, Luigi Carro
    A VLIW low power Java processor for embedded applications. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:157-162 [Conf]
  37. Raimundo S. Barreto, Marília Neves, Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Eduardo Tavares, Ricardo Massa Ferreira Lima
    A formal software synthesis approach for embedded hard real-time systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:163-168 [Conf]
  38. Leandro Buss Becker, Marco A. Wehrmeister, Carlos Eduardo Pereira
    Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:169-174 [Conf]
  39. Márcio Oyamada, Felipe Zschornack, Flávio Rech Wagner
    Accurate software performance estimation using domain classification and neural networks. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:175-180 [Conf]
  40. Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas
    Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:181-185 [Conf]
  41. Michel Leong, Pedro Vasconcelos, Jorge R. Fernandes, Leonel Sousa
    A programmable cellular neural network circuit. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:186-191 [Conf]
  42. Timo Vogt, Norbert Wehn, Philippe Alves
    A multi-standard channel-decoder for base-station applications. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:192-197 [Conf]
  43. Michael J. Thul, Norbert Wehn
    FPGA implementation of parallel turbo-decoders. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:198-203 [Conf]
  44. Cesar Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin
    ParIS: a parameterizable interconnect switch for networks-on-chip. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:204-209 [Conf]
  45. Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner
    A switch architecture and signal synchronization for GALS system-on-chips. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:210-215 [Conf]
  46. Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo
    When reconfigurable architecture meets network-on-chip. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:216-221 [Conf]
  47. Marcel Jacomet, Josef Goette, Venanz Zbinden, Christian Narvaez
    On the dynamic behavior of a novel digital-only sigma--delta A/D converter. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:222-227 [Conf]
  48. David Camarero, Jean-François Naviner, Patrick Loumeau
    Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:228-232 [Conf]
  49. Hans-Dieter Wohlmuth, Daniel Kehrer
    A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:233-236 [Conf]
  50. Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi
    An improved synthesis method for low power hardwired FIR filters. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:237-241 [Conf]
  51. Christian Meise, Christoph Grimm
    A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototyping. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:242-247 [Conf]
  52. Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein
    Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:248-253 [Conf]
  53. Vinícius Correia, André Reis
    Advanced technology mapping for standard-cell generators. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:254-259 [Conf]
  54. Mircea R. Stan, Fatih Hamzaoglu, David Garrett
    Non-Manhattan maze routing. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:260-265 [Conf]
  55. Luiz Alberto P. Melek, Márcio C. Schneider, Carlos Galup-Montoro
    Body-bias compensation technique for SubThreshold CMOS static logic gates. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:267-272 [Conf]
  56. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Low-power dual Vth pseudo dual Vdd domino circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:273-277 [Conf]
  57. Frank Sill, Frank Grassert, Dirk Timmermann
    Low power gate-level design with mixed-Vth (MVT) techniques. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:278-282 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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