Conferences in DBLP
(sbcci) M. Hübner , J. Becker Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. [Citation Graph (0, 0)][DBLP ] Conf ] Valeria Bertacco Formal verification for real-world designs. [Citation Graph (0, 0)][DBLP ] Conf ] Todd M. Austin Robust low power computing in the nanoscale era. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein The re-definition of low power design for HPC: a paradigm shift. [Citation Graph (0, 0)][DBLP ] Conf ] Andrès E. Lagos High performance silicon MEMS for niche market applications. [Citation Graph (0, 0)][DBLP ] Conf ] J. Becker , M. Hübner Run-time reconfigurabilility and other future trends. [Citation Graph (0, 0)][DBLP ] Conf ] Valeria Bertacco Low maintenance verification. [Citation Graph (0, 0)][DBLP ] Conf ] Todd M. Austin Razor: a low-power pipeline based on circuit-level timing speculation. [Citation Graph (0, 0)][DBLP ] Conf ] Victor M. Goulart Ferreira , Lovic Gauthier , Takayuki Kando , Takuma Matsuo , Toshihiko Hashinaga , Kazuaki Murakami REDEFIS: a system with a redefinable instruction set processor. [Citation Graph (0, 0)][DBLP ] Conf ] R. U. R. Mocho , G. H. Sartori , Renato P. Ribas , André Inácio Reis Asynchronous circuit design on reconfigurable devices. [Citation Graph (0, 0)][DBLP ] Conf ] Jozias Oliveira , André Printes , R. C. S. Freire , Elmar U. K. Melcher , Ivan S. S. Silva FPGA architecture for static background subtraction in real time. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel M. Muñoz , Carlos H. Llanos , Mauricio Ayala-Rincón , Rudi van Els , Renato P. Almeida Implementation of dispatching algorithms for elevator systems using reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Thilo Streichert , Christian Strengert , Christian Haubelt , Jürgen Teich Dynamic task binding for hardware/software reconfigurable networks. [Citation Graph (0, 0)][DBLP ] Conf ] Leandro Möller , Rafael Soares , Ewerson Carvalho , Ismael Grehs , Ney Calazans , Fernando Moraes Infrastructure for dynamic reconfigurable systems: choices and trade-offs. [Citation Graph (0, 0)][DBLP ] Conf ] Paulo Sérgio B. do Nascimento , Manoel Eusebio de Lima , Stelita M. da Silva , Jordana L. Seixas Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Masoud Daneshtalab , Ali Afzali-Kusha , Ashkan Sobhani , Zainalabedin Navabi , Mohammad D. Mottaghi , Omid Fatemi Ant colony based routing architecture for minimizing hot spots in NOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Leonel Tedesco , Aline Mello , Leonardo Giacomet , Ney Calazans , Fernando Gehm Moraes Application driven traffic modeling for NoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Mário P. Véstias , Horácio C. Neto Area and performance optimization of a generic network-on-chip architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Sandro A. P. Haddad , Wouter A. Serdijn An ultra low-power class-AB sinh integrator. [Citation Graph (0, 0)][DBLP ] Conf ] Luis H. C. Ferreira , Tales Cleber Pimenta , Robson L. Moreno , Wilhelmus A. V. Noije Ultra low-voltage ultra low-power CMOS threshold voltage reference. [Citation Graph (0, 0)][DBLP ] Conf ] Hamilton Klimach , Márcio C. Schneider , Carlos Galup-Montoro A test chip for automatic MOSFET mismatch characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Girardi , Sergio Bampi Power constrained design optimization of analog circuits based on physical gm/ID characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Pablo Aguirre , Fernando Silveira Bias circuit design for low-voltage cascode transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Fabio Lacerda , Stefano Pietri , Alfredo Olmos A differential switched-capacitor amplifier with programmable gain and output offset voltage. [Citation Graph (0, 0)][DBLP ] Conf ] A. A. Mariano , Dominique Dallet , Yann Deval , Jean-Baptiste Begueret 4GHz continuous-time bandpass delta-sigma modulator for directly high IF A/D conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Ana Isabela Araújo Cunha , Ali M. Niknejad A general domain CMOS companding integrator. [Citation Graph (0, 0)][DBLP ] Conf ] Heiner Giefers , Achim Rettberg Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. [Citation Graph (0, 0)][DBLP ] Conf ] David Déharbe , Sergio Medeiros Aspect-oriented design in systemC: implementation and applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mauricio Ayala-Rincón , Thomas Mailleux Santana SAEPTUM: verification of ELAN hardware specifications using the proof assistant PVS . [Citation Graph (0, 0)][DBLP ] Conf ] Romanelli Lodron Zuim , José T. de Sousa , Claudionor José Nunes Coelho Jr. A fast SAT solver algorithm best suited to reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Leomar S. da Rosa Jr. , Felipe S. Marques , Tiago M. G. Cardoso , Renato P. Ribas , Sachin S. Sapatnekar , André Inácio Reis Fast disjoint transistor networks from BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Assis M. do Nascimento , Marcio F. da S. Oliveira , Marco A. Wehrmeister , Carlos Eduardo Pereira , Flávio Rech Wagner MDA-based approach for embedded software generation from a UML/MOF repository. [Citation Graph (0, 0)][DBLP ] Conf ] Elias Teodoro Silva Jr. , Flávio Rech Wagner , Edison Pignaton Freitas , Carlos Eduardo Pereira Hardware support in a middleware for distributed and real-time embedded applications. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Carlos Schneider Beck , Mateus B. Rutzig , Luigi Carro Cache performance impacts for stack machines in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo A. C. da Costa , Paulo F. Flores , José Monteiro Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo C. G. da Silva , Henri Boudinov , Luigi Carro A cell library for low power high performance CMOS voltage-mode quaternary logic. [Citation Graph (0, 0)][DBLP ] Conf ] Katarina Paulsson , Michael Hübner , Jürgen Becker On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad D. Mottaghi , Ali Afzali-Kusha , Zainalabedin Navabi ByZFAD: a low switching activity architecture for shift-and-add multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Gilson I. Wirth , Ivandro Ribeiro , Michele G. Vieira , Fernanda Gusmão de Lima Kastensmidt Single event transients in dynamic logic. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Roberto Moratelli , Érika F. Cota , Marcelo Lubaszewski A cryptography core tolerant to DFA fault attacks. [Citation Graph (0, 0)][DBLP ] Conf ] Rodrigo Possamai Bastos , Fernanda Lima Kastensmidt , Ricardo Reis Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Pereira Frantz , Fernanda Lima Kastensmidt , Luigi Carro , Érika F. Cota Evaluation of SEU and crosstalk effects in network-on-chip switches. [Citation Graph (0, 0)][DBLP ] Conf ] Margrit R. Krug , Marcelo de Souza Moraes , Marcelo S. Lubaszewski Using a software testing technique to identify registers for partial scan implementation. [Citation Graph (0, 0)][DBLP ] Conf ] André V. Fidalgo , Manuel G. Gericota , Gustavo R. Alves , José M. Ferreira Using NEXUS compliant debuggers for real time fault injection on microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Renato Fernandes Hentschke , Guilherme Flach , Felipe Pinto , Ricardo Reis Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Daniele Bonomi , Giorgio Boselli , Gabriella Trucco , Valentino Liberali Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando da Rocha Paixão Cortes , Eric E. Fabris , Sergio Bampi A band-pass Gm-C Filter design based on gm/ID methodology and characterization. [Citation Graph (0, 0)][DBLP ] Conf ] 