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Conferences in DBLP

International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) (asplos)
1982 (conf/asplos/82)

  1. Justin R. Rattner
    Hardware/Software Cooperation in the iAPX-423. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:1- [Conf]
  2. John L. Hennessy, Norman P. Jouppi, Forest Baskett, Thomas R. Gross, John Gill
    Hardware/Software Tradeoffs for Increased Performance. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:2-11 [Conf]
  3. James W. Rymarczyk
    Coding Guidelines for Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:12-19 [Conf]
  4. Richard K. Johnsson, John D. Wick
    An Overview of the Mesa Processor Architecture. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:20-29 [Conf]
  5. Alan D. Berenbaum, Michael W. Condry, Priscilla M. Lu
    The Operating System and Language Support Features of the BELLMAC-32 Microprocessor. [Citation Graph (1, 0)][DBLP]
    ASPLOS, 1982, pp:30-38 [Conf]
  6. George Radin
    The 801 Minicomputer. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:39-47 [Conf]
  7. David R. Ditzel, Hubert R. McLellan
    Register Allocation for Free: The C Machine Stack Cache. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:48-56 [Conf]
  8. Samuel P. Harbison
    An Architectural Alternative to Optimizing Compilers. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:57-65 [Conf]
  9. Butler W. Lampson
    Fast Procedure Calls. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:66-76 [Conf]
  10. Douglas W. Jones
    Systematic Protection Mechanism Design. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:77-80 [Conf]
  11. Karl Reed
    On a General Property of Memory Mapping Tables. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:81-86 [Conf]
  12. Robert P. Cook, Nitin Donde
    An Experiment to Improve Operand Addressing. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:87-91 [Conf]
  13. Akira Fusaoka, Masaharu Hirayama
    Compiler Chip: A Hardware Implementation of Compiler. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:92-95 [Conf]
  14. B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt
    Architectural Support for the Efficient Generation of Code for Horizontal Architectures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:96-99 [Conf]
  15. R. E. McLear, D. M. Scheibelhut, E. Tammaru
    Guidelines for Creating a Debuggable Processor. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:100-106 [Conf]
  16. Maurice V. Wilkes
    Hardware Support for Memory Protection: Capability Implementations. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:107-116 [Conf]
  17. Fred J. Pollack, George W. Cox, Dan W. Hammerstrom, Kevin C. Kahn, Konrad K. Lai, Justin R. Rattner
    Supporting Ada Memory Management in the iAPX-432. [Citation Graph (2, 0)][DBLP]
    ASPLOS, 1982, pp:117-131 [Conf]
  18. Jean-Paul Sansonnet, Michel Castan, Christian Percebois, D. Botella, J. Perez
    Direct Execution of Lisp on a List-Directed Architecture. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:132-139 [Conf]
  19. Mark Scott Johnson
    Some Requirements for Architectural Support of Software Debugging. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:140-148 [Conf]
  20. C. A. Middleburg
    The Effect of the PDP-11 Architecture on Code Generation for Chill. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:149-157 [Conf]
  21. Richard E. Sweet, James G. Sandman Jr.
    Empirical Analysis of the Mesa Instruction Set. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:158-166 [Conf]
  22. Gene McDaniel
    An Analysis of a Mesa Instruction Set Using Dynamic Instruction Frequencies. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:167-176 [Conf]
  23. Cheryl A. Wiecek
    A Case Study of VAX-11 Instruction Set Usage for Compiler Execution. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1982, pp:177-184 [Conf]
  24. Mamoru Maekawa, Ken Sakamura, Chiaki Ishikawa
    Firmware Structure and Architectural Support for Monitors, Vertical Migration and User Microprogramming. [Citation Graph (1, 0)][DBLP]
    ASPLOS, 1982, pp:185-194 [Conf]
  25. Noriyuki Kamibayashi, H. Ogawana, K. Nagayama, Hideo Aiso
    Heart: An Operating System Nucleus Machine Implemented by Firmware. [Citation Graph (1, 0)][DBLP]
    ASPLOS, 1982, pp:195-204 [Conf]
  26. Sudhir Ahuja, Abhaya Asthana
    A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling. [Citation Graph (1, 0)][DBLP]
    ASPLOS, 1982, pp:205-209 [Conf]
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