Conferences in DBLP
(sbcci) Grant Martin SystemC: From Language to Applications, from Tools to Methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Lysaght System-Level Design for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Luiz Franca-Neto High-Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-Package. [Citation Graph (0, 0)][DBLP ] Conf ] Julio Arlindo Pinto Azevedo , Tales Cleber Pimenta Design of a Low Noise Amplifier for CDMA Transceivers at 900MHz in CMOS 0.35 µm. [Citation Graph (0, 0)][DBLP ] Conf ] Elkim Roa , Joao Navarro Soares , Wilhelmus A. M. Van Noije A Methodology for CMOS Low Noise Ampli.er Design. [Citation Graph (0, 0)][DBLP ] Conf ] Pablo Aguirre , Fernando Silveira Design of a Reusable Rail-to-Rail Operational Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Salvador Pinillos Gimenez , Marcelo Antonio Pavanello , J. A. Martino , S. Adriaensen , Denis Flandre Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Damiani , Andrei Y. Selchenko Boolean Technology Mapping Based on Logic Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Augé , François Donnet , Frédéric Pétrot Retiming Finite State Machines to Control Hardened Data-Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitri Maslov , Gerhard W. Dueck , D. Michael Miller Simplification of Toffoli Networks via Templates. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Martin SystemC and the Future of Design Languages: Opportunities for Users and Research. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo A. C. da Costa , Sergio Bampi , José C. Monteiro A New Pipelined Array Architecture for Signed Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Sumeer Goel , Mohamed A. Elgamel , Magdy A. Bayoumi Novel Design Methodology for High-Performance XOR-XNOR Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Achim Rettberg , Florian Dittmann , Mauro Cesar Zanella , Thomas Lehmann Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Mário P. Véstias , Horácio C. Neto DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Diogo Zandonai , Sergio Bampi , Marcel Bergerman ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Abel Guilhermino S. Filho , Alejandro César Frery , Cristiano C. de Araujo , Haglay Alice , Jorge Cerqueira , Juliana A. Loureiro , Manoel Eusebio de Lima , Maria das Gracas S. Oliveira , Michelle Matos Horta Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Sandro Ferreira , Felipe Haffner , Luis Fernando Pereira , Fernando Moraes Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Nadia Nedjah , Luiza de Macedo Mourelle FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. Stochastic. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Visarius , Johannes Lessmann , Wolfram Hardt , Frank Kelso , Wolfgang Thronicke An XML Format Based Integration Infrastructure for IP Based Design. [Citation Graph (0, 0)][DBLP ] Conf ] Uilian Rafael Feijo Souza , Josue Klafke Sperb , Braulio Adriano de Mello , Flávio Rech Wagner Tangram - Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Julio A. de Oliveira Filho , Manoel Eusebio de Lima , Paulo Romero Martins Maciel , Juliana Moura , Bruno Celso A Fast IP-Core Integration Methodology for SoC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Eric E. Fabris , Luigi Carro , Sergio Bampi A Universal High-Performance Analog Interface for Signal Processing SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Dutta Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems. [Citation Graph (0, 0)][DBLP ] Conf ] João Leonardo Fragoso , Gilles Sicard , Marc Renaudin Automatic Generation of 1-of-M QDI Asynchronous Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Pereira , Antonio Rui Borges , Antonio Ferrari Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tang Lei , Shashi Kumar Algorithms and Tools for Network on Chip Based System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Cesar Albenes Zeferino , Altamiro Amadeu Susin SoCIN: A Parametric and Scalable Network-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] J. B. D. Soldera , Andre Vilas Boas , Alfredo Olmos A Low Ripple Fully Integrated Charge Pump Regulator. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Olmos A Temperature Compensated Fully Trimmable On-Chip IC Oscillator. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando C. Castaldo , Joao Paulo C. Cajueiro , Carlos Alberto dos Reis Bias Dependence of Noise Correlation in MAGFETs. [Citation Graph (0, 0)][DBLP ] Conf ] Esther Rodríguez-Villegas , Alberto Yufera , Adoración Rueda A Charge Correction Cell for FGMOS-Based Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Renato E. B. Poli , Felipe R. Schneider , Renato P. Ribas , André Inácio Reis Unified Theory to Build Cell-Level Transistor Networks from BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Mauricio Ayala-Rincón , Rodrigo B. Nogueira , Carlos H. Llanos , Ricardo P. Jacobi , Reiner W. Hartenstein Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. [Citation Graph (0, 0)][DBLP ] Conf ] George Logothetis , Klaus Schneider , C. Metzler Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Geert Janssen A Consumer Report on BDD Packages. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaldo Azevedo , Rodrigo Soares , Ivan Saraiva Silva A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32. [Citation Graph (0, 0)][DBLP ] Conf ] Achim Rettberg , Mauro Cesar Zanella , Thomas Lehmann , Ulrich Dierkes , Carsten Rustemeier Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Becker , Alexander Thomas , Maik Scheer Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Ryuichi Takahashi , Hajime Ohiwa Situated Learning on FPGA for Superscalar Microprocessor Design Education. [Citation Graph (0, 0)][DBLP ] Conf ] Howard H. Chen , J. Scott Neely , Michael F. Wang , Gricel Co On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed A. Elgamel , Magdy A. Bayoumi Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Janet Meiling Wang , Pinhong Chen , Omar Hafiz A New Continuous Switching Window Computation with Crosstalk Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Renato Fernandes Hentschke , Ricardo Augusto da Luz Reis Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Lysaght Future Design Tools for Platform FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Becker , Michael Hübner , Michael Ullmann Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. [Citation Graph (0, 0)][DBLP ] Conf ] Romanelli Lodron Zuim , Claudionor José Nunes Coelho Jr. , Luiz Fernando Etrusco Moreira , Antônio Otávio Fernandes , José Monteiro da Mata , Diógenes Cecilio da Silva Jr. Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDs. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Lima Ferrão , Gustavo Wilke , Ricardo Augusto da Luz Reis , José Luís Almada Güntzel Improving Critical Path Identification in Functional Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiano Santos , Gustavo Wilke , Cristiano Lazzari , Ricardo Reis , José Luís Almada Güntzel A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Girardi , Fernando da Rocha Paixão Cortes , Eric E. Fabris , Sergio Bampi Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio J. Ginés , Eduardo J. Peralías , Adoración Rueda Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. [Citation Graph (0, 0)][DBLP ] Conf ] Faress Tissafi-Drissi , Ian O'Connor , Fabien Mieyeville , Frédéric Gaffiot Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Negreiros , Erik Schüler , Luigi Carro , Altamiro Amadeu Susin Testing RF Signal Paths Using Spectral Analysis and Subsampling. [Citation Graph (0, 0)][DBLP ] Conf ] J. Pérez , Matteo Sonza Reorda , Massimo Violante Accurate Dependability Analysis of CAN-Based Networked Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Haubelt , Dirk Koch , Jürgen Teich ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio C. S. Beck Filho , Júlio C. B. de Mattos , Flávio Rech Wagner , Luigi Carro CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Ney Laert Vilar Calazans , Edson I. Moreno , Fabiano Hessel , Vitor M. da Rosa , Fernando Moraes , Everton Carara From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] 