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Conferences in DBLP

2003 (conf/sbcci/2003)

  1. Grant Martin
    SystemC: From Language to Applications, from Tools to Methodologies. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:3- [Conf]
  2. Patrick Lysaght
    System-Level Design for FPGAs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:4- [Conf]
  3. Luiz Franca-Neto
    High-Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-Package. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:5- [Conf]
  4. Julio Arlindo Pinto Azevedo, Tales Cleber Pimenta
    Design of a Low Noise Amplifier for CDMA Transceivers at 900MHz in CMOS 0.35 µm. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:9-13 [Conf]
  5. Elkim Roa, Joao Navarro Soares, Wilhelmus A. M. Van Noije
    A Methodology for CMOS Low Noise Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:14-19 [Conf]
  6. Pablo Aguirre, Fernando Silveira
    Design of a Reusable Rail-to-Rail Operational Amplifier. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:20-25 [Conf]
  7. Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, J. A. Martino, S. Adriaensen, Denis Flandre
    Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:26-0 [Conf]
  8. Maurizio Damiani, Andrei Y. Selchenko
    Boolean Technology Mapping Based on Logic Decomposition. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:35-40 [Conf]
  9. Ivan Augé, François Donnet, Frédéric Pétrot
    Retiming Finite State Machines to Control Hardened Data-Paths. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:41-46 [Conf]
  10. Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:47-52 [Conf]
  11. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Simplification of Toffoli Networks via Templates. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:53-0 [Conf]
  12. Grant Martin
    SystemC and the Future of Design Languages: Opportunities for Users and Research. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:61- [Conf]
  13. Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro
    A New Pipelined Array Architecture for Signed Multiplication. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:65-70 [Conf]
  14. Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
    Novel Design Methodology for High-Performance XOR-XNOR Circuit Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:71-0 [Conf]
  15. Achim Rettberg, Florian Dittmann, Mauro Cesar Zanella, Thomas Lehmann
    Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:79-84 [Conf]
  16. Mário P. Véstias, Horácio C. Neto
    DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:85-0 [Conf]
  17. Diogo Zandonai, Sergio Bampi, Marcel Bergerman
    ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:93-98 [Conf]
  18. Abel Guilhermino S. Filho, Alejandro César Frery, Cristiano C. de Araujo, Haglay Alice, Jorge Cerqueira, Juliana A. Loureiro, Manoel Eusebio de Lima, Maria das Gracas S. Oliveira, Michelle Matos Horta
    Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:99-104 [Conf]
  19. Sandro Ferreira, Felipe Haffner, Luis Fernando Pereira, Fernando Moraes
    Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:105-110 [Conf]
  20. Nadia Nedjah, Luiza de Macedo Mourelle
    FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. Stochastic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:111-0 [Conf]
  21. Markus Visarius, Johannes Lessmann, Wolfram Hardt, Frank Kelso, Wolfgang Thronicke
    An XML Format Based Integration Infrastructure for IP Based Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:119-124 [Conf]
  22. Uilian Rafael Feijo Souza, Josue Klafke Sperb, Braulio Adriano de Mello, Flávio Rech Wagner
    Tangram - Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation Environment. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:125-130 [Conf]
  23. Julio A. de Oliveira Filho, Manoel Eusebio de Lima, Paulo Romero Martins Maciel, Juliana Moura, Bruno Celso
    A Fast IP-Core Integration Methodology for SoC Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:131-136 [Conf]
  24. Eric E. Fabris, Luigi Carro, Sergio Bampi
    A Universal High-Performance Analog Interface for Signal Processing SOCs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:137-0 [Conf]
  25. Santanu Dutta
    Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:145- [Conf]
  26. João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
    Automatic Generation of 1-of-M QDI Asynchronous Adders. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:149-154 [Conf]
  27. Artur Pereira, Antonio Rui Borges, Antonio Ferrari
    Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:155-0 [Conf]
  28. Tang Lei, Shashi Kumar
    Algorithms and Tools for Network on Chip Based System Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:163-168 [Conf]
  29. Cesar Albenes Zeferino, Altamiro Amadeu Susin
    SoCIN: A Parametric and Scalable Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:169-0 [Conf]
  30. J. B. D. Soldera, Andre Vilas Boas, Alfredo Olmos
    A Low Ripple Fully Integrated Charge Pump Regulator. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:177-180 [Conf]
  31. Alfredo Olmos
    A Temperature Compensated Fully Trimmable On-Chip IC Oscillator. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:181-186 [Conf]
  32. Fernando C. Castaldo, Joao Paulo C. Cajueiro, Carlos Alberto dos Reis
    Bias Dependence of Noise Correlation in MAGFETs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:187-190 [Conf]
  33. Esther Rodríguez-Villegas, Alberto Yufera, Adoración Rueda
    A Charge Correction Cell for FGMOS-Based Circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:191-0 [Conf]
  34. Renato E. B. Poli, Felipe R. Schneider, Renato P. Ribas, André Inácio Reis
    Unified Theory to Build Cell-Level Transistor Networks from BDDs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:199-204 [Conf]
  35. Mauricio Ayala-Rincón, Rodrigo B. Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
    Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:205-210 [Conf]
  36. George Logothetis, Klaus Schneider, C. Metzler
    Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:211-216 [Conf]
  37. Geert Janssen
    A Consumer Report on BDD Packages. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:217-0 [Conf]
  38. Arnaldo Azevedo, Rodrigo Soares, Ivan Saraiva Silva
    A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:225-230 [Conf]
  39. Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Ulrich Dierkes, Carsten Rustemeier
    Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:231-236 [Conf]
  40. Jürgen Becker, Alexander Thomas, Maik Scheer
    Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:237-242 [Conf]
  41. Ryuichi Takahashi, Hajime Ohiwa
    Situated Learning on FPGA for Superscalar Microprocessor Design Education. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:243-0 [Conf]
  42. Howard H. Chen, J. Scott Neely, Michael F. Wang, Gricel Co
    On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:251-255 [Conf]
  43. Mohamed A. Elgamel, Magdy A. Bayoumi
    Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:256-260 [Conf]
  44. Janet Meiling Wang, Pinhong Chen, Omar Hafiz
    A New Continuous Switching Window Computation with Crosstalk Noise. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:261-266 [Conf]
  45. Renato Fernandes Hentschke, Ricardo Augusto da Luz Reis
    Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:267-0 [Conf]
  46. Patrick Lysaght
    Future Design Tools for Platform FPGAs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:275-0 [Conf]
  47. Jürgen Becker, Michael Hübner, Michael Ullmann
    Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:283-288 [Conf]
  48. Romanelli Lodron Zuim, Claudionor José Nunes Coelho Jr., Luiz Fernando Etrusco Moreira, Antônio Otávio Fernandes, José Monteiro da Mata, Diógenes Cecilio da Silva Jr.
    Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:289-0 [Conf]
  49. Daniel Lima Ferrão, Gustavo Wilke, Ricardo Augusto da Luz Reis, José Luís Almada Güntzel
    Improving Critical Path Identification in Functional Timing Analysis. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:297-302 [Conf]
  50. Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel
    A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:303-0 [Conf]
  51. Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi
    Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:311-316 [Conf]
  52. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:317-322 [Conf]
  53. Faress Tissafi-Drissi, Ian O'Connor, Fabien Mieyeville, Frédéric Gaffiot
    Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:323-328 [Conf]
  54. Marcelo Negreiros, Erik Schüler, Luigi Carro, Altamiro Amadeu Susin
    Testing RF Signal Paths Using Spectral Analysis and Subsampling. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:329-0 [Conf]
  55. J. Pérez, Matteo Sonza Reorda, Massimo Violante
    Accurate Dependability Analysis of CAN-Based Networked Systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:337-342 [Conf]
  56. Christian Haubelt, Dirk Koch, Jürgen Teich
    ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:343-348 [Conf]
  57. Antonio C. S. Beck Filho, Júlio C. B. de Mattos, Flávio Rech Wagner, Luigi Carro
    CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:349-354 [Conf]
  58. Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara
    From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:355-0 [Conf]
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