Conferences in DBLP
Niklaus Wirth Hardware Architectures for Programming Languages and Programming Languages for Hardware Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Beck , Bob Kasten , Shreekant S. Thakkar VLSI Assist For a Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Bisiani , Alessandro Forin Architectural Support for Multilanguage Parallel Programming on Heterogeneous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Richard F. Rashid , Avadis Tevanian , Michael Young , David B. Golub , Robert V. Baron , David L. Black , William J. Bolosky , Jonathan Chew Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Hayes , Martin E. Fraeman , Robert L. Williams , Thomas Zaremba An Architecture for the Direct Execution of the Forth Programming Language. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Steenkiste , John L. Hennessy Tags and Type Checking in Lisp: Hardware and Software Approaches. [Citation Graph (0, 0)][DBLP ] Conf ] Jack W. Davidson , Richard A. Vaughan The Effect of Instruction Set Complexity on Program Size and Memory Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Russell R. Atkinson , Edward M. McCreight The Dragon Processor. [Citation Graph (0, 0)][DBLP ] Conf ] James R. Goodman Coherency for Multiprocessor Virtual Address Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas A. Cargill , Bart N. Locanthi Cheap Hardware Support for Software Debugging and Profiling. [Citation Graph (0, 0)][DBLP ] Conf ] C. J. Georgiou , S. L. Palmer , P. L. Rosenfeld An Experimental Coprocessor for Implementing Persistant Objects on an IBM 4381. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel J. Magenheimer , Liz Peters , Karl Pettis , Dan Zuras Integer Multiplication and Division on the HP Precision Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] David W. Wall , Michael L. Powell The Mahler Experience: Using and Intermediate Language as the Machine Description. [Citation Graph (0, 0)][DBLP ] Conf ] Shlomo Weiss , James E. Smith A Study of Scalar Compilation Techniques for Pipelined Supercomputers. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Bush , A. Dain Samples , David Ungar , Paul N. Hilfinger Compiling Smalltalk-80 to a RISC. [Citation Graph (0, 0)][DBLP ] Conf ] Fred C. Chow , Steven Correll , Mark I. Himelstein , Earl Killian , Larry Weber How Many Addressing Modes are Enough? [Citation Graph (0, 0)][DBLP ] Conf ] Henry Massalin Superoptimizer - A Look at the Smallest Program. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuo Taki , Katsuto Nakajima , Hiroshi Nakashima , Morihiro Ikeda Performance and Architectural Evaluation of the PSI Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Gaetano Borriello , Andrew R. Cherenson , Peter B. Danzig , Michael N. Nelson RISCs versus CISCs for Prolog: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Richard B. Kieburtz A RISC Architecture for Symbolic Computation. [Citation Graph (1, 0)][DBLP ] Conf ] David R. Ditzel , Hubert R. McLellan Design Tradeoffs to Support the C Programming Language in the CRISP Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Charles P. Thacker , Lawrence C. Stewart Firefly: A Multiprocessor Workstation. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas W. Clark Pipelining and Performance in the VAX 8800 Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Colwell , Robert P. Nix , John J. O'Donnell , David B. Papworth , Paul K. Rodman A VLIW Architecture for a Trace Scheduling Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Levinthal , Pat Hanrahan , Mike Paquette , Jim Lawson Parallel Computers for Graphics Applications. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Smith , G. E. Dermer , B. D. Vanderwarn , S. D. Klinger , C. M. Rozewski , D. L. Fowler , K. R. Scidmore , James Laudon The ZS-1 Central Processor. [Citation Graph (0, 0)][DBLP ] Conf ] 