Conferences in DBLP

Software and Compilers for Embedded Systems (scopes)
2003 (conf/scopes/2003)

1. James C. Dehnert
   The Transmeta Crusoe: VLIW Embedded in CISC. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:1- [Conf]
   
2. Qin Zhao, Bart Mesman, Henk Corporaal
   Limited Address Range Architecture for Reducing Code Size in Embedded Processors. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:2-16 [Conf]
   
3. Warren Cheung, William S. Evans, Jeremy Moses
   Predicated Instructions for Code Compaction. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:17-32 [Conf]
   
4. Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson
   Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:33-48 [Conf]
   
5. Erik Eckstein, Oliver König, Bernhard Scholz
   Code Instruction Selection Based on SSA-Graphs. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:49-65 [Conf]
   
6. Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai
   A Code Selection Method for SIMD Processors with PACK Instructions. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:66-80 [Conf]
   
7. Björn Decker 0002, Daniel Kästner
   Reconstructing Control Flow from Predicated Assembly Code. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:81-100 [Conf]
   
8. Stefaan Himpe, Francky Catthoor, Geert Deconinck
   Control Flow Analysis for Recursion Removal. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:101-116 [Conf]
   
9. Litong Song, Krishna M. Kavi, Ron Cytron
   An Unfolding-Based Loop Optimization Technique. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:117-132 [Conf]
   
10. Gang-Ryung Uh
    Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:133-150 [Conf]
    
11. Yunheung Paek, Minwook Ahn, Soonho Lee
    Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:151-166 [Conf]
    
12. Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie
    Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:167-181 [Conf]
    
13. Arshad Jhumka, Neeraj Suri, Martin Hiller
    A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant Programs. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:182-197 [Conf]
    
14. Hiroo Ishikawa, Tatsuo Nakajima
    A Case Study on a Component-Based System and Its Configuration. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:198-210 [Conf]
    
15. Kirk Schloegel, David Oglesby, Eric Engstrom, Devesh Bhatt
    Composable Code Generation for Model-Based Development. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:211-225 [Conf]
    
16. Ioannis Charitakis, Dionisios N. Pnevmatikatos, Evangelos P. Markatos, Kostas G. Anagnostakis
    Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:226-239 [Conf]
    
17. Johan Runeson, Sven-Olof Nyström
    Retargetable Graph-Coloring Register Allocation for Irregular Architectures. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:240-254 [Conf]
    
18. Dae-Hwan Kim, Hyuk-Jae Lee
    Fine-Grain Register Allocation Based on a Global Spill Costs Analysis. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:255-269 [Conf]
    
19. V. V. N. S. Sarvani, R. Govindarajan
    Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:270-284 [Conf]
    
20. Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
    Improving Offset Assignment through Simultaneous Variable Coalescing. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:285-297 [Conf]
    
21. Raimund Kirner, Peter P. Puschner
    Transformation of Meta-Information by Abstract Co-interpretation. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:298-312 [Conf]
    
22. Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor
    Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:313-328 [Conf]
    
23. Kevin Casey, David Gregg, M. Anton Ertl, Andrew Nisbet
    Towards Superinstructions for Java Interpreters. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:329-343 [Conf]
    
24. Ming-Yung Ko, Shuvra S. Bhattacharyya
    Partitioning for DSP Software Synthesis. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:344-358 [Conf]
    
25. Viera Sipková
    Efficient Variable Allocation to Dual Memory Banks of DSPs. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:359-372 [Conf]
    
26. Diego Andrade, Basilio B. Fraguela, Ramon Doallo
    Cache Behavior Modeling of Codes with Data-Dependent Conditionals. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:373-387 [Conf]
    
27. Marco Garatti
    FICO: A Fast Instruction Cache Optimizer. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:388-402 [Conf]