Conferences in DBLP

Symposium on Asynchronous Circuits and Systems (async)
2001 (conf/async/2001)

1. Bill Athas
   Asynchronous Design and the Pursuit of Low Power. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:2-0 [Conf]
   
2. Mike J. G. Lewis, L. E. M. Brackenbury
   Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:4-14 [Conf]
   
3. P. A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber
   A Low-Power Self-Timed Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:15-24 [Conf]
   
4. Gianluca Cornetta, Jordi Cortadella
   A Multi-Radix Approach to Asynchronous Division. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:25-0 [Conf]
   
5. David W. Lloyd, Jim D. Garside
   A Practical Comparison of Asynchronous Design Styles. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:36-45 [Conf]
   
6. Ivan E. Sutherland, Scott Fairbanks
   GasP: A Minimal FIFO Control. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:46-53 [Conf]
   
7. Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri
   PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:54-0 [Conf]
   
8. Chris J. Myers, Hans M. Jacobson
   Efficient Exact Two-Level Hazard-Free Logic Minimization. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:64-73 [Conf]
   
9. Robert Berks, Radu Negulescu
   Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:74-0 [Conf]
   
10. Ad M. G. Peeters, Kees van Berkel
    Synchronous Handshake Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:86-95 [Conf]
    
11. Rajit Manohar
    An Analysis of Reshuffled Handshaking Expansions. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:96-0 [Conf]
    
12. Joep L. W. Kessels, Ad M. G. Peeters, Torsten Kramer, Markus Feuser, Klaus Ully
    Designing an Asynchronous Bus Interface. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:108-117 [Conf]
    
13. W. J. Bainbridge, Stephen B. Furber
    Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:118-126 [Conf]
    
14. Alexandre Yakovlev, Fei Xia, Delong Shang
    Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:127-0 [Conf]
    
15. Kevin Normoyle
    Where are the Async Millionaires? [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:138-0 [Conf]
    
16. Tony Werner, Venkatesh Akella
    An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:140-151 [Conf]
    
17. Daranee Hormdee, Jim D. Garside
    AMULET3i Cache Architecture. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:152-161 [Conf]
    
18. Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno
    Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:162-172 [Conf]
    
19. William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland
    FLEETzero: An Asynchronous Switching Experiment. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:173-0 [Conf]
    
20. Ivan E. Sutherland, Jon K. Lexau
    Designing Fast Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:184-193 [Conf]
    
21. Jo C. Ebergen
    Squaring the FIFO in GasP. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:194-205 [Conf]
    
22. Mark R. Greenstreet, Brian de Alwis
    How to Achieve Worst-Case Performance. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:206-0 [Conf]
    
23. Ajay Koche
    Testing Asynchronous Circuits: Help is on the Way! [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:218-0 [Conf]