Conferences in DBLP
David A. Kearney , Neil W. Bergmann Performance evaluation of asynchronous logic pipelines with data dependent processing delays. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio J. Acosta , Manuel J. Bellido , Manuel Valencia , Angel Barriga Barrios , Raúl Jiménez , José L. Huertas New CMOS VLSI linear self-timed architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jelio T. Yantchev , C. G. Huang , Mark B. Josephs , I. M. Nedelchev Low-latency asynchronous FIFO buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Yakovlev , Victor Varshavsky , Vyacheslav Marakhovsky , Alexei L. Semenov Designing an asynchronous pipeline token ring interface. [Citation Graph (0, 0)][DBLP ] Conf ] Joep L. W. Kessels VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player. [Citation Graph (0, 0)][DBLP ] Conf ] Ad M. G. Peeters , Kees van Berkel Single-rail handshake circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rik van de Wiel High-level test evaluation of asynchronous circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kees van Berkel , Ronan Burgess , Joep L. W. Kessels , Ad M. G. Peeters , Marly Roncken , Frits D. Schalij , Rik van de Wiel A single-rail re-implementation of a DCC error detector using a generic standard-cell library. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew M. Bailey , Mark B. Josephs Sequencer circuits for VLSI programming. [Citation Graph (0, 0)][DBLP ] Conf ] C. Farnsworth , David A. Edwards , Jianwei Liu , S. S. Sikand A hybrid asynchronous system design environment. [Citation Graph (0, 0)][DBLP ] Conf ] Kees van Berkel , Ferry Huberts , Ad M. G. Peeters Stretching quasi delay insensitivity by means of extended isochronic forks. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Negulescu , Janusz A. Brzozowski Relative liveness: from intuition to automated verification. [Citation Graph (0, 0)][DBLP ] Conf ] Chantal Ykman-Couvreur , Bill Lin Optimised state assignment for asynchronous circuit synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Oriol Roig , Jordi Cortadella , Enric Pastor Hierarchical gate-level verification of speed-independent circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chris J. Myers , Peter A. Beerel , Teresa H. Y. Meng Technology mapping of timed circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz A. Brzozowski , Kaamran Raahemifar Testing C-elements is not elementary. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Khoche , Erik Brunvand Testing self-timed circuits using partial scan. [Citation Graph (0, 0)][DBLP ] Conf ] Eckhard Grass , S. Jones Asynchronous circuits based on multiple localised current-sensing completion detection. [Citation Graph (0, 0)][DBLP ] Conf ] Shannon V. Morton , Sam S. Appleton , Michael J. Liebelt ECSTAC: a fast asynchronous microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] D. K. Arvind , Robert D. Mullins , Vinod E. F. Rebello Micronets: a model for decentralising control in asynchronous processor architectures. [Citation Graph (0, 0)][DBLP ] Conf ] C. J. Elston , D. B. Christianson , P. A. Findlay , G. B. Steven Hades-towards the design of an asynchronous superscalar processor. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Hsing Chien , Mark A. Franklin , Tienyo Pan , Prithvi Prabhu ARAS: asynchronous RISC architecture simulator. [Citation Graph (0, 0)][DBLP ] Conf ] 