The SCEAS System
Navigation Menu

Conferences in DBLP

Symposium on Asynchronous Circuits and Systems (async)
2004 (conf/async/2004)

  1. Christer Svensson
    Synchronous Latency Insensitive Design. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:3- [Conf]
  2. Jo C. Ebergen, Daniel Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins
    A Fast and Energy-Efficient Stack. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:7-16 [Conf]
  3. John Teifel, Rajit Manohar
    Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:17-27 [Conf]
  4. Radu Negulescu
    General Testers for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:28-38 [Conf]
  5. Scott Fairbanks, Simon W. Moore
    Analog Micropipeline Rings for High Precision Timing. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:41-50 [Conf]
  6. Jo C. Ebergen, Jonathan Gainsley, Paul Cunningham
    Transistor Sizing: How to Control the Speed and Energy Consumption of a Circuit. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:51-61 [Conf]
  7. Masashi Imai, Metehan Özcan, Takashi Nanya
    Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:62-71 [Conf]
  8. David Fang, Rajit Manohar
    Non-Uniform Access Asynchronous Register Files. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:75-85 [Conf]
  9. Alireza Kaviani
    Phase Alignment Using Asynchronous State Machines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:86-94 [Conf]
  10. Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel
    High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:95-105 [Conf]
  11. Martin Jenkner
    Contacting Biological Cells with Electronic Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:109- [Conf]
  12. Xiaohua Kong, Radu Negulescu
    Bolstering Faith in GasP Circuits through Formal Verification. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:113-124 [Conf]
  13. Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton
    A General Purpose Behavioural Asynchronous Synthesis System. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:125-134 [Conf]
  14. Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers
    Synthesis of Speed Independent Circuits Based on Decomposition. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:135-145 [Conf]
  15. Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou
    Handshake Protocols for De-Synchronization. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:149-158 [Conf]
  16. Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas
    Hiding Synchronization Delays in a GALS Processor Microarchitecture. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:159-169 [Conf]
  17. Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou
    Data Synchronization Issues in GALS SoCs. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:170-180 [Conf]
  18. Ad M. G. Peeters
    Bringing Handshake Technology to the Open Market. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:183- [Conf]
  19. Recep O. Ozdag, Peter A. Beerel
    A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:187-197 [Conf]
  20. F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin
    Asynchronous FIR Filters: Towards a New Digital Processing Chain. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:198-206 [Conf]
  21. Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury
    An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:207-215 [Conf]
  22. Nisrine Saadallah, Xiaohua Kong, Radu Negulescu
    High-Speed Reduced Stack Dual Lock Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:219-228 [Conf]
  23. Mika Nyström, Elaine Ou, Alain J. Martin
    An Eight-Bit Divider Implemented in Asynchronous Pulse Logic. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:229-239 [Conf]
  24. Ron Ho, Jonathan Gainsley, Robert J. Drost
    Long Wires and Asynchronous Control. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:240-249 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002