|
|
Conferences in DBLP
- Phillip Restle, Kenneth L. Shepard
New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:- [Conf]
- Robert J. Drost, Ivan E. Sutherland
Proximity Communication and Time. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:- [Conf]
- Robert P. Colwell
Deep Pipelines vs. Risk and Power Walls. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:- [Conf]
- Suwen Yang, Brian D. Winters, Mark R. Greenstreet
Energy Efficient Surfing. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:2-11 [Conf]
- Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland
GasP Control for Domino Circuits. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:12-22 [Conf]
- Tin Wai Kwan, Maitham Shams
Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:23-32 [Conf]
- Tobias Bjerregaard, Jens Sparsø
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:34-43 [Conf]
- Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar
An Asynchronous Router for Multiple Service Levels Networks on Chip. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:44-53 [Conf]
- Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:54-63 [Conf]
- Joep L. W. Kessels
Register Communication between Mutually Asynchronous Domains. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:66-75 [Conf]
- Milos Krstic, Eckhard Grass, Christian Stahl
Request-Driven GALS Technique for Wireless Communication System. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:76-85 [Conf]
- Scott Fairbanks, Simon W. Moore
Self-Timed Circuitry for Global Clocking. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:86-96 [Conf]
- Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens
Modeling and Verifying Circuits Using Generalized Relative Timing. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:98-108 [Conf]
- Vassilis Zebilis, Christos P. Sotiriou
Controlling Event Spacing in Self-Timed Rings. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:109-115 [Conf]
- Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald
Delay Insensitive Encoding and Power Analysis: A Balancing Act. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:116-125 [Conf]
- Justin Hensley, Anselmo Lastra, Montek Singh
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:128-137 [Conf]
- Yee William Li, Kenneth L. Shepard, Yannis P. Tsividis
Continuous-Time Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:138-143 [Conf]
- Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar
BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:144-154 [Conf]
- Wonjin Jang, Alain J. Martin
SEU-Tolerant QDI Circuits. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:156-165 [Conf]
- Frank te Beest, Ad M. G. Peeters
A Multiplexor Based Test Method for Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:166-175 [Conf]
- Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers
High Level Synthesis of Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:178-189 [Conf]
- Nikolai Starodoubtsev, Sergei Bystrov
Behavior and Synthesis of Two-Input Gate Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:190-200 [Conf]
- Frederic Worm, Patrick Thiran, Paolo Ienne
A Unified Coding Framework for Delay-Insensitivity. [Citation Graph (0, 0)][DBLP]
ASYNC, 2005, pp:201-211 [Conf]
|
