Conferences in DBLP
William S. Coates , Jon K. Lexau , Ian W. Jones , Scott M. Fairbanks , Ivan E. Sutherland A FIFO Data Switch Design Experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Renaudin , Pascal Vivet , Frédéric Robin ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] N. C. Paver , P. Day , C. Farnsworth , D. L. Jackson , W. A. Lien , Jianwei Liu A Low-Power, Low-Noise, Configurable Self-Timed DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Benes , Steven M. Nowick , Andrew Wolfe A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Theobald , Steven M. Nowick An Implicit Method for Hazard-Free Two-Level Logic Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin W. James , Kenneth Y. Yun Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Chun Chou , Peter A. Beerel , Ran Ginosar , Rakefet Kol , Chris J. Myers , Shai Rotem , Ken S. Stevens , Kenneth Y. Yun Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hans van Gageldonk , Kees van Berkel , Ad M. G. Peeters , Daniel Baumann , Daniel Gloor , Gerhard Stegmann An Asynchronous Low-Power 80C51 Microcontroller. [Citation Graph (0, 0)][DBLP ] Conf ] Kåre T. Christensen , Peter Jensen , Peter Korger , Jens Sparsø The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. [Citation Graph (0, 0)][DBLP ] Conf ] W. J. Bainbridge , Stephen B. Furber Asynchronous Macrocell Interconnect using MARBLE. [Citation Graph (0, 0)][DBLP ] Conf ] P. T. Røine An Asynchronous PRBS Error Checker for Testing High-Speed Self-Clocked Serial Links. [Citation Graph (0, 0)][DBLP ] Conf ] Tarik Ono-Tesfaye , Christoph Kern , Mark R. Greenstreet Verifying a Self-Timed Divider. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Negulescu , Ad M. G. Peeters Verification of Speed-Dependences in Single-Rail Handshake Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Verhoeff Analyzing Specifications for Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Willem C. Mallon , Jan Tijmen Udding Building Finite Automata from DI Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw J. Piestrak Membership Test Logic for Delay-Insensitive Codes. [Citation Graph (0, 0)][DBLP ] Conf ] D. J. Kinniment , Alexandre Yakovlev , Fei Xia , B. Gao Towards Asynchronous A-D Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce W. Hunt , Kenneth S. Stevens , Bruce W. Suter , Donald S. Gelosh A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ross Smith , Karl Fant , Dave Parker , Rick Stephani , Ching-Yi Wang An Asynchronous 2-D Discrete Cosine Transform Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jo C. Ebergen , Scott Fairbanks , Ivan E. Sutherland Predicting Performance of Micropipelines Using Charlie Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Aiguo Xie , Peter A. Beerel Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshio Kameda , Stanislav Polonsky , Masaaki Maezawa , Takashi Nanya Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Z. John Deng , Steve R. Whiteley , Theodore Van Duzer , José A. Tierno Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology. [Citation Graph (0, 0)][DBLP ] Conf ] 