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Conferences in DBLP

Symposium on Asynchronous Circuits and Systems (async)
1998 (conf/async/1998)

  1. William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland
    A FIFO Data Switch Design Experiment. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:4-0 [Conf]
  2. Marc Renaudin, Pascal Vivet, Frédéric Robin
    ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:22-31 [Conf]
  3. N. C. Paver, P. Day, C. Farnsworth, D. L. Jackson, W. A. Lien, Jianwei Liu
    A Low-Power, Low-Noise, Configurable Self-Timed DSP. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:32-42 [Conf]
  4. Martin Benes, Steven M. Nowick, Andrew Wolfe
    A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:43-0 [Conf]
  5. Michael Theobald, Steven M. Nowick
    An Implicit Method for Hazard-Free Two-Level Logic Minimization. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:58-69 [Conf]
  6. Kevin W. James, Kenneth Y. Yun
    Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:70-79 [Conf]
  7. Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun
    Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:80-0 [Conf]
  8. Hans van Gageldonk, Kees van Berkel, Ad M. G. Peeters, Daniel Baumann, Daniel Gloor, Gerhard Stegmann
    An Asynchronous Low-Power 80C51 Microcontroller. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:96-107 [Conf]
  9. Kåre T. Christensen, Peter Jensen, Peter Korger, Jens Sparsø
    The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:108-0 [Conf]
  10. W. J. Bainbridge, Stephen B. Furber
    Asynchronous Macrocell Interconnect using MARBLE. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:122-132 [Conf]
  11. P. T. Røine
    An Asynchronous PRBS Error Checker for Testing High-Speed Self-Clocked Serial Links. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:133-0 [Conf]
  12. Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet
    Verifying a Self-Timed Divider. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:146-158 [Conf]
  13. Radu Negulescu, Ad M. G. Peeters
    Verification of Speed-Dependences in Single-Rail Handshake Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:159-0 [Conf]
  14. Tom Verhoeff
    Analyzing Specifications for Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:172-183 [Conf]
  15. Willem C. Mallon, Jan Tijmen Udding
    Building Finite Automata from DI Specifications. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:184-193 [Conf]
  16. Stanislaw J. Piestrak
    Membership Test Logic for Delay-Insensitive Codes. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:194-0 [Conf]
  17. D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao
    Towards Asynchronous A-D Conversion. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:206-215 [Conf]
  18. Bruce W. Hunt, Kenneth S. Stevens, Bruce W. Suter, Donald S. Gelosh
    A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:216-223 [Conf]
  19. Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang
    An Asynchronous 2-D Discrete Cosine Transform Chip. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:224-0 [Conf]
  20. Jo C. Ebergen, Scott Fairbanks, Ivan E. Sutherland
    Predicting Performance of Micropipelines Using Charlie Diagrams. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:238-246 [Conf]
  21. Aiguo Xie, Peter A. Beerel
    Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:247-0 [Conf]
  22. Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya
    Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:262-273 [Conf]
  23. Z. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno
    Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:274-0 [Conf]
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