Conferences in DBLP
Marco A. Peña , Jordi Cortadella , Enric Pastor , Alex Kondratyev Formal Verification of Safety Properties in Timed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Willem C. Mallon On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism. [Citation Graph (0, 0)][DBLP ] Conf ] Igor Benko , Jo C. Ebergen Composing Snippets. [Citation Graph (0, 0)][DBLP ] Conf ] Joep L. W. Kessels , Gerrit den Besten , Ad M. G. Peeters , Torsten Kramer , Volker Timm Applying Asynchronous Circuits in Contactless Smart Cards. [Citation Graph (0, 0)][DBLP ] Conf ] George S. Taylor , Simon W. Moore , Steve Wilcox , Peter Robinson An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Muttersbach , Thomas Villiger , Wolfgang Fichtner Practical Design of Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Marly Roncken , Ken S. Stevens , Rajesh Pendurkar , Shai Rotem , Parimal Pal Chaudhuri CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Philip P. Shirvani , Subhasish Mitra , Jo C. Ebergen , Marly Roncken DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Blunno , Luciano Lavagno Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. [Citation Graph (0, 0)][DBLP ] Conf ] Hans M. Jacobson , Erik Brunvand , Ganesh Gopalakrishnan , Prabhakar Kudva High-Level Asynchronous System Design Using the ACK Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Euiseok Kim , Jeong-Gun Lee , Dong-Ik Lee Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Michiel M. Ligthart , Karl Fant , Ross Smith , Alexander Taubin , Alex Kondratyev Asynchronous Design Using Commercial HDL Synthesis Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre V. Bystrov , D. J. Kinniment , Alexandre Yakovlev Priority Arbiters. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Molnar , Ian W. Jones Simple Circuits that Work for Complicated Reasons. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Xia , Alexandre Yakovlev , Delong Shang , Alexandre V. Bystrov , Alexandre V. Koelmans , D. J. Kinniment Asynchronous Communication Mechanisms Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jim D. Garside , W. J. Bainbridge , Andrew Bardsley , David M. Clark , David A. Edwards , Stephen B. Furber , David W. Lloyd , S. Mohammadi , J. S. Pepper , Steve Temple , J. V. Woods , Jianwei Liu , O. Petli AMULET3i - An Asynchronous System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Mike J. G. Lewis , L. E. M. Brackenbury An Instruction Buffer for a Low-Power DSP. [Citation Graph (0, 0)][DBLP ] Conf ] O. Hauck , A. Katoch , Sorin A. Huss VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Montek Singh , Steven M. Nowick High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Tiberiu Chelcea , Steven M. Nowick Low-Latency Asynchronous FIFO's Using Token Rings. [Citation Graph (0, 0)][DBLP ] Conf ] 