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Conferences in DBLP

Symposium on Asynchronous Circuits and Systems (async)
2000 (conf/async/2000)

  1. Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev
    Formal Verification of Safety Properties in Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:2-11 [Conf]
  2. Willem C. Mallon
    On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:12-22 [Conf]
  3. Igor Benko, Jo C. Ebergen
    Composing Snippets. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:23-0 [Conf]
  4. Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm
    Applying Asynchronous Circuits in Contactless Smart Cards. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:36-44 [Conf]
  5. George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson
    An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:45-51 [Conf]
  6. Jens Muttersbach, Thomas Villiger, Wolfgang Fichtner
    Practical Design of Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:52-0 [Conf]
  7. Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri
    CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:62-72 [Conf]
  8. Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken
    DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:73-0 [Conf]
  9. Ivan Blunno, Luciano Lavagno
    Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:84-92 [Conf]
  10. Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva
    High-Level Asynchronous System Design Using the ACK Framework. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:93-103 [Conf]
  11. Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee
    Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:104-113 [Conf]
  12. Michiel M. Ligthart, Karl Fant, Ross Smith, Alexander Taubin, Alex Kondratyev
    Asynchronous Design Using Commercial HDL Synthesis Tools. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:114-0 [Conf]
  13. Alexandre V. Bystrov, D. J. Kinniment, Alexandre Yakovlev
    Priority Arbiters. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:128-137 [Conf]
  14. Charles E. Molnar, Ian W. Jones
    Simple Circuits that Work for Complicated Reasons. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:138-149 [Conf]
  15. Fei Xia, Alexandre Yakovlev, Delong Shang, Alexandre V. Bystrov, Alexandre V. Koelmans, D. J. Kinniment
    Asynchronous Communication Mechanisms Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:150-0 [Conf]
  16. Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, J. V. Woods, Jianwei Liu, O. Petli
    AMULET3i - An Asynchronous System-on-Chip. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:162-175 [Conf]
  17. Mike J. G. Lewis, L. E. M. Brackenbury
    An Instruction Buffer for a Low-Power DSP. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:176-0 [Conf]
  18. O. Hauck, A. Katoch, Sorin A. Huss
    VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:188-0 [Conf]
  19. Montek Singh, Steven M. Nowick
    High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:198-0 [Conf]
  20. Tiberiu Chelcea, Steven M. Nowick
    Low-Latency Asynchronous FIFO's Using Token Rings. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:210-0 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002