Conferences in DBLP

Symposium on Asynchronous Circuits and Systems (async)
1999 (conf/async/1999)

1. Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
   Verification of Delayed-Reset Domino Circuits Using ATACS. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:3-12 [Conf]
   
2. Per Arne Karlsen, Per Torstein Røine
   A Timing Verifier and Timing Profiler for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:13-0 [Conf]
   
3. Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury
   Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:27-35 [Conf]
   
4. Alexander Taubin, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno
   Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:36-0 [Conf]
   
5. Jim D. Garside, Stephen B. Furber, S.-H. Chung
   AMULET3 Revealed. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:51-59 [Conf]
   
6. Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun
   RAPPID: An Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:60-70 [Conf]
   
7. David W. Lloyd, Jim D. Garside, D. A. Gilbert
   Memory Faults in Asynchronous Microprocessors. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:71-0 [Conf]
   
8. Tod Amon, Henrik Hulgaard
   Symbolic Time Separation of Events. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:83-93 [Conf]
   
9. Aiguo Xie, Sangyun Kim, Peter A. Beerel
   Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:94-107 [Conf]
   
10. Tomohiro Yoneda, Hiroshi Ryu
    Timed Trace Theoretic Verification Using Partial Order Reduction. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:108-0 [Conf]
    
11. Rajit Manohar, Tak-Kwan Lee, Alain J. Martin
    Projection: A Synthesis Technique for Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:125-134 [Conf]
    
12. Marc Renaudin, Pascal Vivet, Frédéric Robin
    A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:135-144 [Conf]
    
13. Jochen Beister, Gernot Eckstein, Ralf Wollowski
    From STG to Extended-Burst-Mode Machines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:145-0 [Conf]
    
14. Bill Coates, Jo C. Ebergen, Jon K. Lexau, Scott Fairbanks, Ian W. Jones, Alex Ridgway, David Harris, Ivan E. Sutherland
    A Counterflow Pipeline Experiment. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:161-172 [Conf]
    
15. Mark R. Greenstreet, Tarik Ono-Tesfaye
    A Fast, asP*, RGD Arbiter. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:173-185 [Conf]
    
16. Mark R. Greenstreet
    Real-Time Merging. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:186-0 [Conf]
    
17. David A. Kearney
    Theoretical Limits on the Data Dependent Performance of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:201-207 [Conf]
    
18. Ken S. Stevens, Shai Rotem, Ran Ginosar
    Relative Timing. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:208-218 [Conf]
    
19. O. Hauck, M. Garg, Sorin A. Huss
    Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:219-0 [Conf]
    
20. Willem C. Mallon, Jan Tijmen Udding, Tom Verhoeff
    Analysis and Applications of the XDI model. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:231-242 [Conf]
    
21. Märt Saarepera, Tomohiro Yoneda
    A Self-Timed Implementation of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:243-0 [Conf]