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Conferences in DBLP

Symposium on Asynchronous Circuits and Systems (async)
2002 (conf/async/2002)

  1. Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster
    Synchronous Interlocked Pipelines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:3-12 [Conf]
  2. Recep O. Ozdag, Peter A. Beerel
    High-Speed QDI Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:13-22 [Conf]
  3. Rajit Manohar, Clinton Kelly IV, John Teifel, David Fang, David Biermann
    Energy-Efficient Pipelines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:23-0 [Conf]
  4. Mark R. Greenstreet, Brian D. Winters
    A Negative-Overhead, Self-Timed Pipeline. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:37-46 [Conf]
  5. Mark R. Greenstreet, Anthony Winstanley, Aurelien Garivier
    An Event Spacing Experiment. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:47-0 [Conf]
  6. Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters, Paul Wielage
    Clock Synchronization through Handshake Signalling. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:59-68 [Conf]
  7. George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson
    Point to Point GALS Interconnect. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:69-75 [Conf]
  8. Eckhard Grass, Bodhisatya Sarker, Koushik Maharatna
    A Dual-Mode Synchronous/Asynchronous CORDIC Processor. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:76-83 [Conf]
  9. José A. Tierno, Sergey Rylov, Alexander Rylyakov, Montek Singh, Steven M. Nowick
    An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:84-0 [Conf]
  10. Rohan Angrish, Supratik Chakraborty
    Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delay. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:99-108 [Conf]
  11. Metehan Özcan, Masashi Imai, Takashi Nanya
    Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:109-114 [Conf]
  12. Peter A. Beerel, Ken S. Stevens, Hoshik Kim
    Relative Timing Based Verification of Timed Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:115-0 [Conf]
  13. Alexandre V. Bystrov, Alexandre Yakovlev
    Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:127-136 [Conf]
  14. Rudolf H. Mak
    Design and Performance Analysis of Buffers: A Constructive Approach. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:137-148 [Conf]
  15. Alex Kondratyev, Oriol Roig, Lawrence Neukom, Karl Fant, Alexander Taubin
    Checking Delay-Insensitivity: 104 Gates and Beyond. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:149-0 [Conf]
  16. Frank te Beest, Kees van Berkel, Ad M. G. Peeters
    Adding Synchronous and LSSD Modes to Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:161-170 [Conf]
  17. Amy Streich, Alex Kondratyev, Lief Sorensen
    Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:171-180 [Conf]
  18. Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:181-189 [Conf]
  19. D. J. Kinniment, Oleh V. Maevsky, Gordon Russell, Alexandre Yakovlev, Alexandre V. Bystrov
    On-Chip Structures for Timing Measurements and Test. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:190-0 [Conf]
  20. W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana
    SPA - A Synthesisable Amulet Core for Smartcard pplications. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:201-210 [Conf]
  21. Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor
    Improving Smart Card Security Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:211-0 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002