Conferences in DBLP
Jean-Pierre Schoellkopf ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System Architecture. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:- [Conf ] Nobuo Karaki Asynchronous Design: An Enabler for Flexible Microelectronics. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:- [Conf ] Ferdinand Peper Asynchronous Architectures for Nanometer Scales. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:- [Conf ] David Kinniment , Keith Heron , Gordon Russell Measuring Deep Metastability. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:2-11 [Conf ] Filipp Akopyan , Rajit Manohar , Alyssa B. Apsel A Level-Crossing Flash Asynchronous Analog-to-Digital Converter. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:12-22 [Conf ] Jo C. Ebergen , Alex Chow , Bill Coates , Justin Schauer , David Hopkins An Asynchronous High-Throughput Control Circuit For Proximity Communication. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:23-33 [Conf ] Song Peng , Rajit Manohar Self-Healing Asynchronous Arrays. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:34-45 [Conf ] Gennette Gill , Ankur Agiwal , Montek Singh , Feng Shi , Yiorgos Makris Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:46-56 [Conf ] Feng Shi , Yiorgos Makris A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:57-67 [Conf ] Masashi Imai , Takashi Nanya A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:68-77 [Conf ] L. Necchi , Luciano Lavagno , Davide Pandini , Laura Vanzago An ultra-low energy asynchronous processor for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:78-85 [Conf ] D. Caucheteux , Edith Beigné , Elisabeth Crochon , Marc Renaudin AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:86-97 [Conf ] Mark R. Greenstreet , Jihong Ren Surfing Interconnect. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:98-106 [Conf ] Crescenzo D'Alessandro , Delong Shang , Alexandre V. Bystrov , Alexandre Yakovlev , Oleg V. Maevsky Multiple-Rail Phase-Encoding for NoC. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:107-116 [Conf ] Rostislav (Reuven) Dobkin , Ran Ginosar , Avinoam Kolodny Fast Asynchronous Shift Register for Bit-Serial Communication. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:117-127 [Conf ] Cheoljoo Jeong , Steven M. Nowick Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:128-137 [Conf ] W. B. Toms , David A. Edwards , Andrew Bardsley Synthesising Heterogeneously Encoded Systems. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:138-149 [Conf ] Frank K. Gürkaynak , Stephan Oetiker , Hubert Kaeslin , Norbert Felber , Wolfgang Fichtner GALS at ETH Zurich: Success or Failure. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:150-159 [Conf ] Joycee Mekie , Supratik Chakraborty , Dinesh K. Sharma , Girish Venkataramani , P. S. Thiagarajan Interface Design for Rationally Clocked GALS Systems. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:160-171 [Conf ] Edith Beigné , Pascal Vivet Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:172-183 [Conf ] Peter A. Beerel , Nam-Hoon Kim , Andrew Lines , Mike Davies Slack Matching Asynchronous Designs. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:184-194 [Conf ] Piyush Prakash , Alain J. Martin Slack Matching Quasi Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:195-204 [Conf ]