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Conferences in DBLP

Symposium on Asynchronous Circuits and Systems (async)
2007 (conf/async/2007)

  1. Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny
    High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:3-14 [Conf]
  2. Jo C. Ebergen, Steve Furber, Arash Saifhashemi
    Notes On Pulse Signaling. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:15-24 [Conf]
  3. Suwen Yang, Mark R. Greenstreet, Jihong Ren
    A Jitter Attenuating Timing Chain. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:25-38 [Conf]
  4. Andrew Lines
    The Vortex: A Superscalar Asynchronous Processor. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:39-48 [Conf]
  5. Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel
    Design of a High-Speed Asynchronous Turbo Decoder. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:49-59 [Conf]
  6. Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley
    Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:60-72 [Conf]
  7. Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet
    Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:73-82 [Conf]
  8. Mark B. Josephs
    Gate-level modelling and verification of asynchronous circuits using CSPM and FDR. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:83-94 [Conf]
  9. Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener
    The Design of a Genetic Muller C-Element. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:95-104 [Conf]
  10. Crescenzo D'Alessandro, Andrey Mokhov, Alexandre V. Bystrov, Alexandre Yakovlev
    Delay/Phase Regeneration Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:105-116 [Conf]
  11. Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein
    Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:117-128 [Conf]
  12. Melinda Y. Agyekum, Steven M. Nowick
    A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:129-142 [Conf]
  13. Alex Chow, William S. Coates, David Hopkins
    A Configurable Asynchronous Pseudorandom Bit Sequence Generator. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:143-152 [Conf]
  14. Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks
    On-chip samplers for test and debug of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:153-162 [Conf]
  15. Nikolaos Minas, David Kinniment, Keith Heron, Gordon Russell
    A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:163-174 [Conf]
  16. Robert D. Mullins, Simon W. Moore
    Demystifying Data-Driven and Pausible Clocking Schemes. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:175-185 [Conf]
  17. Amitava Mitra, William F. McLaughlin, Steven M. Nowick
    Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:186-195 [Conf]
  18. Wade L. Williams, Philip E. Madrid, Scott C. Johnson
    Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:196-204 [Conf]
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