Conferences in DBLP
Rostislav (Reuven) Dobkin , Yevgeny Perelman , Tuvia Liran , Ran Ginosar , Avinoam Kolodny High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:3-14 [Conf ] Jo C. Ebergen , Steve Furber , Arash Saifhashemi Notes On Pulse Signaling. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:15-24 [Conf ] Suwen Yang , Mark R. Greenstreet , Jihong Ren A Jitter Attenuating Timing Chain. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:25-38 [Conf ] Andrew Lines The Vortex: A Superscalar Asynchronous Processor. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:39-48 [Conf ] Pankaj Golani , Georgios D. Dimou , Mallika Prakash , Peter A. Beerel Design of a High-Speed Asynchronous Turbo Decoder. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:49-59 [Conf ] Andrew M. Scott , Mark E. Schuelein , Marly Roncken , Jin-Jer Hwan , John Bainbridge , John R. Mawer , David L. Jackson , Andrew Bardsley Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:60-72 [Conf ] Gwen Salaün , Wendelin Serwe , Yvain Thonnart , Pascal Vivet Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:73-82 [Conf ] Mark B. Josephs Gate-level modelling and verification of asynchronous circuits using CSPM and FDR. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:83-94 [Conf ] Nam-Phuong D. Nguyen , Hiroyuki Kuwahara , Chris J. Myers , James P. Keener The Design of a Genetic Muller C-Element. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:95-104 [Conf ] Crescenzo D'Alessandro , Andrey Mokhov , Alexandre V. Bystrov , Alexandre Yakovlev Delay/Phase Regeneration Circuits. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:105-116 [Conf ] Tiberiu Chelcea , Girish Venkataramani , Seth Copen Goldstein Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:117-128 [Conf ] Melinda Y. Agyekum , Steven M. Nowick A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:129-142 [Conf ] Alex Chow , William S. Coates , David Hopkins A Configurable Asynchronous Pseudorandom Bit Sequence Generator. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:143-152 [Conf ] Frankie Liu , Ron Ho , Robert J. Drost , Scott Fairbanks On-chip samplers for test and debug of asynchronous circuits. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:153-162 [Conf ] Nikolaos Minas , David Kinniment , Keith Heron , Gordon Russell A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:163-174 [Conf ] Robert D. Mullins , Simon W. Moore Demystifying Data-Driven and Pausible Clocking Schemes. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:175-185 [Conf ] Amitava Mitra , William F. McLaughlin , Steven M. Nowick Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:186-195 [Conf ] Wade L. Williams , Philip E. Madrid , Scott C. Johnson Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:196-204 [Conf ]