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Conferences in DBLP

System-Level Interconnect Prediction (slip)
2000 (conf/slip/2000)

  1. Phillip Christie
    Managing interconnect resources (tutorial). [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:1-51 [Conf]
  2. Denis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis
    Theoretical limits for signal reflections due to inductance for on-chip interconnections. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:55-60 [Conf]
  3. Mariagrazia Graziano, Marco Delaurenti, Maurizio Zamboni
    Power supply design parameters prediction for high performance IC design flows. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:61-67 [Conf]
  4. Imed Ben Dhaou, Hannu Tenhunen
    Energy efficient high-speed on-chip signaling in deep-submicron CMOS technology. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:69-76 [Conf]
  5. Dennis Sylvester
    Measurement techniques and interconnect estimation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:79-81 [Conf]
  6. Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur
    Performance analysis and technology of 3-D ICs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:85-90 [Conf]
  7. Srinivas Bodapati, Farid N. Najm
    Pre-layout estimation of individual wire lengths. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:93-98 [Conf]
  8. Dirk Stroobandt, Herwig Van Marck
    Efficient representation of interconnection length distributions using generating polynomials. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:99-105 [Conf]
  9. Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
    Prediction of interconnect fan-out distribution using Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:107-112 [Conf]
  10. Andrew B. Kahng, Dirk Stroobandt
    Wiring layer assignments with consistent stage delays. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:115-122 [Conf]
  11. James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:123-127 [Conf]
  12. Peng Li, Pranab K. Nag, Wojciech Maly
    Cost based tradeoff analysis of standard cell designs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:129-135 [Conf]
  13. Louis Scheffer, Eric Nequist
    Why interconnect prediction doesn't work. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:139-144 [Conf]
  14. Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
    Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:147-148 [Conf]
  15. Amir H. Farrahi
    Estimation and removal or routing congestion (discussion session). [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:149- [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002