The SCEAS System
Navigation Menu

Conferences in DBLP

System-Level Interconnect Prediction (slip)
2001 (conf/slip/2001)

  1. Dirk Stroobandt
    A priori system-level interconnect prediction: Rent's rule and wire length distribution models. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:3-21 [Conf]
  2. Xiaojian Yang, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Wirelength estimation based on rent exponents of partitioning and placement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:25-31 [Conf]
  3. Peter Verplaetse, Joni Dambre, Dirk Stroobandt, Jan Van Campenhout
    On partitioning vs. placement rent properties. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:33-40 [Conf]
  4. Dirk Stoobandt
    Multi-terminal nets do change conventional wire length distribution models. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:41-48 [Conf]
  5. Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout
    On rent's rule for rectangular regions. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:49-56 [Conf]
  6. Ralph H. J. M. Otten, Giuseppe S. Garcea
    Are wires plannable? [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:59-66 [Conf]
  7. Kenneth Rose
    A comprehensive look at system level model. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:69-87 [Conf]
  8. Kenneth D. Boese, Andrew B. Kahng, Stefanus Mantik
    On the relevance of wire load models. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:91-98 [Conf]
  9. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu
    Interconnect implications of growth-based structural models for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:99-106 [Conf]
  10. Arifur Rahman, Shamik Das, Anantha Chandrakasan, Rafael Reif
    Wiring requirement and three-dimensional integration of field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:107-113 [Conf]
  11. Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh
    Interconnect complexity-aware FPGA placement using Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:115-121 [Conf]
  12. Michael D. Hutton
    Interconnect prediction for programmable logic devices. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:125-131 [Conf]
  13. José Pineda de Gyvez
    Yield modeling and BEOL fundamentals. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:135-163 [Conf]
  14. Phillip Christie, José Pineda de Gyvez
    Pre-layout prediction of interconnect manufacturability. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:167-173 [Conf]
  15. James D. Z. Ma, Lei He
    Simultaneous signal and power routing under K model. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:175-182 [Conf]
  16. Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Hierarchical power supply noise evaluation for early power grid design prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:183-188 [Conf]
  17. Shih-Hsu Huang
    An effective low power design methodology based on interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:189-194 [Conf]
  18. André DeHon
    Rent's rule based switching requirements. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:197-204 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002