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Conferences in DBLP

System-Level Interconnect Prediction (slip)
2002 (conf/slip/2002)

  1. Stephen E. Krufka, Phillip Christie
    Terminal optimization analysis for functional block re-use. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:3-8 [Conf]
  2. Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout
    Getting more out of Donath's hierarchical model for interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:9-16 [Conf]
  3. Tianpei Zhang, Sachin S. Sapatnekar
    Optimized pin assignment for lower routing congestion after floorplanning phase. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:17-21 [Conf]
  4. Amit Singh, Malgorzata Marek-Sadowska
    FPGA interconnect planning. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:23-30 [Conf]
  5. Steven L. Teig
    The X architecture: not your father's diagonal wiring. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:33-37 [Conf]
  6. Sudhakar Muddu
    Estimation needs for future networking systems interconnect. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:41-44 [Conf]
  7. Andrey V. Mezhiba, Eby G. Friedman
    Scaling trends of on-chip Power distribution noise. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:47-53 [Conf]
  8. Sani R. Nassif, Onsi Fakhouri
    Technology trends in power-grid-induced noise. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:55-59 [Conf]
  9. Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim
    Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:61-68 [Conf]
  10. Ingrid Verbauwhede, M.-C. Frank Chang
    Reconfigurable interconnect for next generation systems. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:71-74 [Conf]
  11. Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda
    Early probabilistic noise estimation for capacitively coupled interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:77-83 [Conf]
  12. Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng
    Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:85-89 [Conf]
  13. Muzammil Iqbal, Ahmed Sharkawy, Usman Hameed, Phillip Christie
    Stochastic wire length sampling for cycle time estimation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:91-96 [Conf]
  14. Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie
    Wire layer geometry optimization using stochastic wire sampling. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:97-102 [Conf]
  15. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
    Interconnect exploration for future wire dominated technologies. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:105-106 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002