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Conferences in DBLP

System-Level Interconnect Prediction (slip)
2004 (conf/slip/2004)

  1. Reinaldo A. Bergamaschi
    Early and accurate analysis of SoCs: oxymoron or real? [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:3-6 [Conf]
  2. Nir Magen, Avinoam Kolodny, Uri Weiser, Nachum Shamir
    Interconnect-power dissipation in a microprocessor. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:7-13 [Conf]
  3. Bipin Rajendran, Pawan Kapur, Krishna Saraswat, R. Fabian, W. Pease
    Self-consistent power/performance/reliability analysis for copper interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:17-22 [Conf]
  4. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
    Investigation of performance metrics for interconnect stack architectures. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:23-29 [Conf]
  5. Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li
    Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:31-38 [Conf]
  6. Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex
    Interconnect width selection for deep submicron designs using the table lookup method. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:41-44 [Conf]
  7. Vikas Chandra, Anthony Xu, Herman Schmit
    A low power approach to system level pipelined interconnect design. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:45-52 [Conf]
  8. Tapani Ahonen, David A. Sigüenza-Tortosa, Hong Bin, Jari Nurmi
    Topology optimization for application-specific networks-on-chip. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:53-60 [Conf]
  9. Dmitri B. Chklovskii
    Evolution as the blind engineer: wiring minimization in the brain. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:63- [Conf]
  10. Ajay Joshi, Jeffrey A. Davis
    A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:64-68 [Conf]
  11. Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson
    NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:69-75 [Conf]
  12. Ian O'Connor
    Optical solutions for system-level interconnect. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:79-88 [Conf]
  13. Arvind Kumar, Sandip Tiwari
    Defect tolerance for nanocomputer architecture. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:89-96 [Conf]
  14. Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix
    Prediction of interconnect adjacency distribution: derivation, validation, and applications. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:99-106 [Conf]
  15. Tao Wan, Malgorzata Chrzanowska-Jeske
    Prediction of interconnect net-degree distribution based on Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:107-114 [Conf]
  16. Maurizio Martina, Guido Masera
    A statistical model for estimating the effect of process variations on crosstalk noise. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:115-120 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002