Conferences in DBLP
Ron Ho High-performance ULSI: the real limiter to interconnect scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Takumi Uezono , Junpei Inoue , Takanori Kyogoku , Kenichi Okada , Kazuya Masu Prediction of delay time for future LSI using on-chip transmission line interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Guoqing Chen , Hui Chen , Mikhail Haurylau , Nicholas Nelson , Philippe M. Fauchet , Eby G. Friedman , David H. Albonesi Predictions of CMOS compatible on-chip optical interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] J. Balachandran , Steven Brebels , G. Carchon , T. Webers , Walter De Raedt , Bart Nauwelaers , Eric Beyne Package level interconnect options. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine Shu-Min Li , Chung-Len Lee , Yao-Wen Chang , Chauchin Su , Jwu E. Chen Multilevel full-chip routing with testability and yield enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj Dealing with interconnect process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Mary Yvonne Lanzerotti , Giovanni Fiorenza , Rick A. Rand Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. [Citation Graph (0, 0)][DBLP ] Conf ] Wim Heirman , Joni Dambre , Christof Debaes , Hugo Thienpont , Dirk Stroobandt , Jan Van Campenhout Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Hathaway Dealing with the spatio-temporal interactions among transient power, supply noise and timing. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Su Kwon , Payam Lajevardi , Anantha P. Chandrakasan , Frank Honoré , Donald E. Troxel A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. [Citation Graph (0, 0)][DBLP ] Conf ] Viet H. Nguyen , Phillip Christie The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Lienig Interconnect and current density stress: an introduction to electromigration-aware design. [Citation Graph (0, 0)][DBLP ] Conf ] Chiu-Wing Sham , Evangeline F. Y. Young Congestion prediction in early stages. [Citation Graph (0, 0)][DBLP ] Conf ] Jurjen Westra , Patrick Groeneveld Is probabilistic congestion estimation worthwhile? [Citation Graph (0, 0)][DBLP ] Conf ] 