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Conferences in DBLP

System-Level Interconnect Prediction (slip)
2005 (conf/slip/2005)

  1. Ron Ho
    High-performance ULSI: the real limiter to interconnect scaling. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:3- [Conf]
  2. Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu
    Prediction of delay time for future LSI using on-chip transmission line interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:7-12 [Conf]
  3. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
    Predictions of CMOS compatible on-chip optical interconnect. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:13-20 [Conf]
  4. J. Balachandran, Steven Brebels, G. Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne
    Package level interconnect options. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:21-27 [Conf]
  5. Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
    Multilevel full-chip routing with testability and yield enhancement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:29-36 [Conf]
  6. N. S. Nagaraj
    Dealing with interconnect process variations. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:39- [Conf]
  7. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
    Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:43-50 [Conf]
  8. Wim Heirman, Joni Dambre, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan Van Campenhout
    Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:51-58 [Conf]
  9. David J. Hathaway
    Dealing with the spatio-temporal interactions among transient power, supply noise and timing. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:61- [Conf]
  10. Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel
    A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:65-72 [Conf]
  11. Viet H. Nguyen, Phillip Christie
    The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:73-78 [Conf]
  12. Jens Lienig
    Interconnect and current density stress: an introduction to electromigration-aware design. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:81-88 [Conf]
  13. Chiu-Wing Sham, Evangeline F. Y. Young
    Congestion prediction in early stages. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:91-98 [Conf]
  14. Jurjen Westra, Patrick Groeneveld
    Is probabilistic congestion estimation worthwhile? [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:99-106 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002