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Conferences in DBLP

System-Level Interconnect Prediction (slip)
2006 (conf/slip/2006)

  1. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
    Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:3-8 [Conf]
  2. Pranav Anbalagan, Jeffrey A. Davis
    A priori prediction of tightly clustered connections based on heuristic classification trees. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:9-15 [Conf]
  3. Andrew B. Kahng, Sherief Reda
    A tale of two nets: studies of wirelength progression in physical design. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:17-24 [Conf]
  4. Louis Scheffer
    An overview of on-chip interconnect variation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:27-28 [Conf]
  5. Andrew B. Kahng, Rasit Onur Topaloglu
    Generation of design guarantees for interconnect matching. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:29-34 [Conf]
  6. Chandu Visweswariah
    Statistical analysis and optimization in the presence of gate and interconnect delay variations. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:37- [Conf]
  7. Wenyi Feng, Jonathan W. Greene
    Post-placement interconnect entropy: how many configuration bits does a programmable logic device need? [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:41-48 [Conf]
  8. Manuel Saldaña, Lesley Shannon, Paul Chow
    The routability of multiprocessor network topologies in FPGAs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:49-56 [Conf]
  9. Wim Heirman, Joni Dambre, Jan M. Van Campenhout
    Congestion modeling for reconfigurable inter-processor networks. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:59-66 [Conf]
  10. Young-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho
    Modeling and analysis of the system bus latency on the SoC platform. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:67-74 [Conf]
  11. Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor
    Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:75-81 [Conf]
  12. Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex
    Impact of interconnect resistance increase on system performance of low power and high performance designs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:85-90 [Conf]
  13. Andrew B. Kahng, Bao Liu, Xu Xu
    Statistical crosstalk aggressor alignment aware interconnect delay calculation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:91-97 [Conf]
  14. J. Balachandran, Steven Brebels, G. Carchon, M. Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne
    Constant impedance scaling paradigm for interconnect synthesis. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:99-105 [Conf]
  15. Prashant Saxena
    The scaling of interconnect buffer needs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:109-112 [Conf]
  16. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:113-120 [Conf]
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