Conferences in DBLP
Yervant Zorian , Juan Antonio Carballo T1: Design for Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Adit D. Singh T2: Statistical Methods for VLSI Test and Burn-in Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Hayes Faults and Tests in Quantum Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas W. Williams Design for Testability: The Path to Deep Submicron. [Citation Graph (0, 0)][DBLP ] Conf ] ATS Steering Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty Improving Logic Test Quality of Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjiv Taneja DFT Aware Layout - Layout Aware DFT. [Citation Graph (0, 0)][DBLP ] Conf ] Advisory Board and Organizing Committee. [Citation Graph (0, 0)][DBLP ] Conf ] TTTC Introduction. [Citation Graph (0, 0)][DBLP ] Conf ] Program Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Reviewers. [Citation Graph (0, 0)][DBLP ] Conf ] Copyright. [Citation Graph (0, 0)][DBLP ] Conf ] Best Paper Awards (2002 and 2003). [Citation Graph (0, 0)][DBLP ] Conf ] TTEP Introduction. [Citation Graph (0, 0)][DBLP ] Conf ] Foreword. [Citation Graph (0, 0)][DBLP ] Conf ] Title Page. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski Embedded Test Technology - Brief History, Current Status, and Future Directions. [Citation Graph (0, 0)][DBLP ] Conf ] Donghoon Han , Abhijit Chatterjee Robust Built-In Test of RF ICs Using Envelope Detectors. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Yan , Adit D. Singh , Gefu Xu Delay Defect Characterization Using Low Voltage Test. [Citation Graph (0, 0)][DBLP ] Conf ] Shalabh Goyal , Michael Purtell Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase , Yoshiyuki Goi , Yoshiyuki Tanaka IDDQ Testing Method using a Scan Pattern for Production Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Ajoy Kumar Palit , Lei Wu , Kishore K. Duganapalli , Walter Anheier , Jürgen Schlöffel A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos D. Liveris , Hai Zhou , Prithviraj Banerjee An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Hekmatpour , Azadeh Salehi Block-based Schema-driven Assertion Generation for Functional Verification. [Citation Graph (0, 0)][DBLP ] Conf ] K. Uday Bhaskar , M. Prasanth , V. Kamakoti , Kailasnath Maneparambil A Framework for Automatic Assembly Program Generator (A2 PG) for Verification and Testing of Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Guangmei Zhang , Chen Rui , Xiaowei Li , Han Congying The Automatic Generation of Basis Set of Path for Path Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yong-sheng Wang , Jin-xiang Wang , Feng-chang Lai , Yizheng Ye Optimal Schemes for ADC BIST Based on Histogram. [Citation Graph (0, 0)][DBLP ] Conf ] A. M. Majid , David C. Keezer , J. V. Karia A 5 Gbps Wafer-Level Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Achintya Halder , Abhijit Chatterjee Low-cost Production Test of BER for Wireless Receivers. [Citation Graph (0, 0)][DBLP ] Conf ] Shaolei Quan , Qiang Qiang , Chin-Long Wey Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Marienfeld , Egor S. Sogomonyan , Vitalij Ocheretnij , Michael Gössel New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Guangyan Huang , Guangmei Zhang , Xiaowei Li , Yunzhan Gong A State Machine for Detecting C/C++ Memory Faults. [Citation Graph (0, 0)][DBLP ] Conf ] S. Biswas , P. Srikanth , R. Jha , S. Mukhopadhyay , A. Patra , D. Sarkar On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Samuel , Rajib Mall Boundary Value Testing based on UML Models. [Citation Graph (0, 0)][DBLP ] Conf ] Jiun-Lang Huang Random Jitter Testing Using Low Tap-Count Delay Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Shae Wu , Chung-Len Lee , Yeong-Jar Chang , Wen Ching Wu Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. [Citation Graph (0, 0)][DBLP ] Conf ] Wichian Sirisaengtaksin , Sandeep K. Gupta A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Pei-Fu Shen , Huawei Li , Yongjun Xu , Xiaowei Li Non-robust Test Generation for Crosstalk-Induced Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Ming-Jing Chen , Hideo Fujiwara Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Chaowen Yu , Sudhakar M. Reddy , Irith Pomeranz Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Tehranipoor , Mehrdad Nourani , Nisar Ahmed Low Transition LFSR for BIST-Based Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Huaguo Liang , Maoxiang Yi , Xiangsheng Fang , Cuiyun Jiang A BIST Scheme Based on Selecting State Generation of Folding Counters. [Citation Graph (0, 0)][DBLP ] Conf ] Tomokazu Yoneda , Hisakazu Takakuwa , Hideo Fujiwara Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Nakamura , Akio Shirokane , Yoshihito Nishizaki , Anis Uzzaman , Vivek Chickermane , Brion L. Keller , Tsutomu Ube , Yoshihiko Terauchi Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Larsson , Erik Larsson , Petru Eles , Zebo Peng SOC Test Scheduling with Test Set Sharing and Broadcasting. [Citation Graph (0, 0)][DBLP ] Conf ] Animesh Datta , Swarup Bhunia , Saibal Mukhopadhyay , Kaushik Roy A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Saibal Mukhopadhyay , Arijit Raychowdhury , Hamid Mahmoodi-Meimand , Kaushik Roy Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Chun Dawn , Jen-Chieh Yeh , Cheng-Wen Wu , Chia-Ching Wang , Yung-Chen Lin , Chao-Hsun Chen Flash Memory Die Sort by a Sample Classification Method. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase , Tatsuya Furukawa Chip Identification using the Characteristic Dispersion of Transistor. [Citation Graph (0, 0)][DBLP ] Conf ] Manan Syal , Michael S. Hsiao , Suriyaprakash Natarajan , Sreejit Chakravarty Untestable Multi-Cycle Path Delay Faults in Industrial Designs. [Citation Graph (0, 0)][DBLP ] Conf ] N. Devtaprasanna , Sudhakar M. Reddy , A. Gunda , P. Krishnamurthy , Irith Pomeranz Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. [Citation Graph (0, 0)][DBLP ] Conf ] I-De Huang , Sandeep K. Gupta Selection of Paths for Delay Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kohei Miyase , Kenta Terashima , Seiji Kajihara , Xiaoqing Wen , Sudhakar M. Reddy On Improving Defect Coverage of Stuck-at Fault Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Shih Ping Lin , Chung-Len Lee , Jwu E. Chen A Scan Matrix Design for Low Power Scan-Based Test. [Citation Graph (0, 0)][DBLP ] Conf ] Youbean Kim , Myung-Hoon Yang , Yong Lee 0002 , Sungho Kang A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Hadi Esmaeilzadeh , Saeed Shamshiri , Pooya Saeedi , Zainalabedin Navabi ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed ElShoukry , Mohammad Tehranipoor , C. P. Ravikumar Partial Gating Optimization for Power Reduction During Test Application. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zou , Wu-Tung Cheng , Sudhakar M. Reddy Bridge Defect Diagnosis with Physical Information. [Citation Graph (0, 0)][DBLP ] Conf ] Yuki Yoshikaw , Satoshi Ohtake , Michiko Inoue , Hideo Fujiwara Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Clouqueur , Hideo Fujiwara , Kewal K. Saluja A Class of Linear Space Compactors for Enhanced Diagnostic. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Kundu , Piet Engelke , Ilia Polian , Bernd Becker On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Hyun Baik , Kewal K. Saluja State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. [Citation Graph (0, 0)][DBLP ] Conf ] Shahrzad Mirkhani , Zainalabedin Navabi Enhancing Fault Simulation Performance by Dynamic Fault Clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Sukanta Das , Hafizur Rahaman , Biplab K. Sikdar Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Tomoo Inoue , Naoki Okamoto , Toshinori Hosokawa , Hideo Fujiwara An Effective Design for Hierarchical Test Generation Based on Strong Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Alok S. Doshi Concurrent Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] V. R. Devanathan Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Iwata , Tomokazu Yoneda , Satoshi Ohtake , Hideo Fujiwara A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Jay Jahangiri , Nilanjan Mukherjee , Wu-Tung Cheng , Subramanian Mahadevan , Ron Press Achieving High Test Quality with Reduced Pin Count Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Kai-Wei Li , Hideo Fujiwara Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. [Citation Graph (0, 0)][DBLP ] Conf ] Shih Ping Lin , Chung-Len Lee , Jwu E. Chen Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Sameer Goel , Rubin A. Parekhji Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Sheng Zhang , Sharad C. Seth , Bhargab B. Bhattacharya Efficient Test Compaction for Pseudo-Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Hsuan Fu , Sying-Jyan Wang Test Data Compression with Partial LFSR-Reseeding. [Citation Graph (0, 0)][DBLP ] Conf ] Debdeep Mukhopadhyay , Shibaji Banerjee , Dipanwita Roy Chowdhury , Bhargab B. Bhattacharya CryptoScan: A Secured Scan Chain Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu Pseudo-Parity Testing with Testable Design. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine Shu-Min Li , Chung-Len Lee , Tagin Jiang , Chauchin Su , Jwu E. Chen Finite State Machine Synthesis for At-Speed Oscillation Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Shinogi , Hiroyuki Yamada , Terumine Hayashi , Shinji Tsuruoka , Tomohiro Yoshikawa A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yinhe Han , Xiaowei Li , Shivakumar Swaminathan , Yu Hu , Anshuman Chandra Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. [Citation Graph (0, 0)][DBLP ] Conf ] Aiman H. El-Maleh , S. Saqib Khursheed , Sadiq M. Sait Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Youhua Shi , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki , Shinji Kimura Low Power Test Compression Technique for Designs with Multiple Scan Chain. [Citation Graph (0, 0)][DBLP ] Conf ] Zhigang Jiang , Sandeep K. Gupta Threshold testing: Covering bridging and other realistic faults. [Citation Graph (0, 0)][DBLP ] Conf ] Biplab K. Sikdar , Arijit Sarkar , Samir Roy , Debesh K. Das Synthesis of Testable Finite State Machine Through Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Swaroop Ghosh , Swarup Bhunia , Kaushik Roy Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Gupta , Tarang Vaish , Santanu Chattopadhyay Flip-flop chaining architecture for power-efficient scan during test application. [Citation Graph (0, 0)][DBLP ] Conf ] Varun Arora , Indranil Sengupta A Unified Approach to Partial Scan Design using Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ilia Polian , Thomas Fiehn , Bernd Becker , John P. Hayes A Family of Logical Fault Models for Reversible Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kedarnath J. Balakrishnan , Nur A. Touba , Srinivas Patil Compressing Functional Tests for Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , Said Hamdioui , Jörg E. Vollrath Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Ji-Xue Xiao , Guang-Ju Chen , Yong-Le Xie Arithmetic Test Strategy for FFT Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuko Kambe , Michiko Inoue , Hideo Fujiwara , Tsuyoshi Iwagaki Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Waayers , Erik Jan Marinissen , Maurice Lousberg IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Rubin A. Parekhji DFT for Low Cost SOC Test. [Citation Graph (0, 0)][DBLP ] Conf ] R. Chandramouli Managing Test and Repair of Embedded Memory Subsystem in SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhu Krishnamurthy The Ultimate Chase. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Iyengar , Phil Nigh Defect-Oriented Test for Ultra-Low DPM. [Citation Graph (0, 0)][DBLP ] Conf ] Hans A. R. Manhaeve Current Testing for Nanotechnologies: A Demystifying Application Perspective.. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh High Level Test Generation for Custom Hardware: An Industrial Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Parvathala High Level Test Generation / SW based Embedded Test. [Citation Graph (0, 0)][DBLP ] Conf ] Subramanian K. Iyer , Jawahar Jain , Debashis Sahoo , Takeshi Shimizu Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. [Citation Graph (0, 0)][DBLP ] Conf ] Kedarnath J. Balakrishnan Emerging Techniques for Test Data Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Nilanjan Mukherjee Improving Test Quality Using Test Data Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Tapan J. Chakraborty Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. [Citation Graph (0, 0)][DBLP ] Conf ] Sasikumar Cherubal Challenges in Next Generation Mixed-Signal IC Production Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Salem Abdennadher , Saghir A. Shaikh Practices in Testing of Mixed-Signal and RF SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Salem Abdennadher , Saghir A. Shaikh Challenges in High Speed Interface Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Chickermane , Brion L. Keller , Kevin McCauley , Anis Uzzaman Practical Aspects of Delay Testing for Nanometer Chips. [Citation Graph (0, 0)][DBLP ] Conf ] T. M. Mak Limitation of structural scan delay test. [Citation Graph (0, 0)][DBLP ] Conf ] Fairuz Zakaria , Zainal Abu Kassim , Melanie Po-Leen Ooi , Serge N. Demidenko Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVST. [Citation Graph (0, 0)][DBLP ] Conf ] 