Conferences in DBLP
Oum-El-Kheir Benkahla , Chouki Aktouf , Chantal Robach Distributed off-line testing of parallel systems. [Citation Graph (0, 0)][DBLP ] Conf ] H. A. Xie , Kevin E. Forward , K. M. Adams , Suthikshn Kumar An SBus Multi-Tracer and its applications. [Citation Graph (0, 0)][DBLP ] Conf ] Yoon-Hwa Choi , Chul Kim Exploitation of parallelism in group probing for testing massively parallel processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Yutaka Hata , Kazuharu Yamato A cellular array designed from a Multiple-valued Decision Diagram and its fault tests. [Citation Graph (0, 0)][DBLP ] Conf ] Yinghua Min , Zhuxing Zhao , Zhongcheng Li Boolean process-an analytical approach to circuit representation (II). [Citation Graph (0, 0)][DBLP ] Conf ] Jwu E. Chen , Chung-Len Lee , Wen-Zen Shen , Beyin Chen Fanout fault analysis for digital logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Branka Medved Rogina , Bozidar Vojnovic Metastability evaluation method by propagation delay distribution measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Zuan Zhang An approach to hierarchy model checking via evaluating CTL hierarchically. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Hideo Tamamoto , Kozo Kinoshita Transistor leakage fault location with ZDDQ measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takahashi , Nobuhiro Yanagida , Yuzo Takamatsu Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing. [Citation Graph (0, 0)][DBLP ] Conf ] Teruhiko Yamada , Koji Yamazaki , Edward J. McCluskey A simple technique for locating gate-level faults in combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nabanita Das , Jayasree Dattagupta A fault location technique and alternate routing in Benes network. [Citation Graph (0, 0)][DBLP ] Conf ] Eiji Harada , Janak H. Patel Overhead reduction techniques for hierarchical fault simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Karen Panetta Lentz , Elias S. Manolakos , Edward C. Czeck On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Pin Kung , Chun-Jieh Huang , Chen-Shang Lin Fast fault simulation for BIST applications. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , P. Huc , Yves Bertrand Serial transistor network modeling for bridging fault simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Winfried Hahn , A. Hagerer , R. Kandlbinder Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Florence Azaïs , Yves Bertrand A design-for-test technique for multistage analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yeong-Ruey Shieh , Cheng-Wen Wu DC control and observation structures for analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rzeszut , Bozena Kaminska , Yvon Savaria A new method for testing mixed analog and digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] A. K. B. A'ain , A. H. Bratt , A. P. Dorey On the development of power supply voltage control testing technique for analogue circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hassan Ihs , Christian Dufaza Tolerance DC bands of CMOS operational amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] S. Nandi , Parimal Pal Chaudhuri Theory and applications of cellular automata for synthesis of easily testable combinational logic. [Citation Graph (0, 0)][DBLP ] Conf ] Seiken Yano Unified scan design with scannable memory arrays. [Citation Graph (0, 0)][DBLP ] Conf ] S. Lavabre , Yves Bertrand , Michel Renovell , Christian Landrault Test configurations to enhance the testability of sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Seiji Kajihara , Kozo Kinoshita Test sequence compaction by reduced scan shift and retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Debesh K. Das , Bhargab B. Bhattacharya Testable design of non-scan sequential circuits using extra logic. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhir K. Jhajharia , Hua Swee Wang Training diploma students on ATE-related module. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Bernard Courtois , Fumiyasu Hirose , Sandip Kundu , Chung-Len Lee , Yinghua Min , P. Pal Chaudhuri Panel: New Research Problems in the Emerging Test Technology. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Gurjeet S. Saund , Nidhi Agrawal A STAFAN-like functional testability measure for register-level circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu , Gercy P. Dias Testability forecasting for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yves Le Traon , Chantal Robach Testability analysis of co-designed systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir Generator choices for delay test. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Static compaction for two-pattern test sets. [Citation Graph (0, 0)][DBLP ] Conf ] Wen Ching Wu , Chung-Len Lee , Jwu E. Chen Identification of robust untestable path delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Dhruva R. Chakrabarti , Ajai Jain An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Udo Mahlstedt , Jürgen Alt , Ingo Hollenbeck Deterministic test generation for non-classical faults on the gate level. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Date , Michinobu Nakao , Kazumi Hatayama A parallel sequential test generation system DESCARTES based on real-valued logic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Inoue , Hideo Fujiwara , Hiroyuki Michinishi , Tokumi Yokohira , Takuji Okamoto Universal test complexity of field-programmable gate arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Balakrishnan , Srimat T. Chakradhar Software transformations for sequential test generation. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir Module level weighted random patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Meng-Lieh Sheu , Chung-Len Lee A programmable multiple-sequence generator for BIST applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Yang Jou An effective BIST design for PLA. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Franklin Fast computation of C-MISR signatures. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Gizopoulos , Antonis M. Paschalis , Yervant Zorian An effective BIST scheme for carry-save and carry-propagate array multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Serge N. Demidenko , Alexander Ivanyukovich , Leonid Makhist , Vincenzo Piuri Error masking in compact testing based on the Hamming code and its modifications. [Citation Graph (0, 0)][DBLP ] Conf ] Ioannis Voyiatzis , Dimitris Nikolos , Antonis M. Paschalis , Constantinos Halatsis , Th. Haniotakis An efficient comparative concurrent Built-In Self-Test technique. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Gaitanis , Panagiotis Kostarakis , Antonis M. Paschalis Totally Self Checking reconfigurable duplication system with separate internal fault indication. [Citation Graph (0, 0)][DBLP ] Conf ] Gosta Pada Biswas , Idranil Sen Gupta Generalized modular design of testable m-out-of-n code checker. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi Y. Busaba , Parag K. Lala A graph coloring based approach for self-checking logic circuit design. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takahashi , Takashi Watanabe , Yuzo Takamatsu Generation of tenacious tests for small gate delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mandyam-Komar Srinivas , Vishwani D. Agrawal , Michael L. Bushnell Functional test generation for path delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Jason P. Hurst , Nick Kanopoulos Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Soumitra Bose , Vishwani D. Agrawal Sequential logic path delay test generation by symbolic analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Ueda , Kozo Kinoshita Low power design and its testability. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Liu , Rafic Z. Makki Power supply current detectability of SRAM defects. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Pagey Fast functional testing of delay-insensitive circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Pagey , Ajay Khoche , Erik Brunvand DFT for fast testing of self-timed control circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mallika De , Bhabani P. Sinha Testing of a parallel ternary multiplier using I/sup 2/L logic. [Citation Graph (0, 0)][DBLP ] Conf ] 