Conferences in DBLP
Qiang Xu , Nicola Nicolici Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yinhe Han , Yu Hu , Huawei Li , Xiaowei Li , Anshuman Chandra Rapid and Energy-Efficient Testing for Embedded Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Jianhui Xing , Hong Wang , Shiyuan Yang Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Aristides Efthymiou , John Bainbridge , Douglas A. Edwards Adding Testability to an Asynchronous Interconnect for GALS SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Shaing-Jer Hsu , Chia-Ming Ho Test Power Reduction with Multiple Capture Orders. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiqiang You , Ken-ichi Yamaguchi , Michiko Inoue , Jacob Savir , Hideo Fujiwara Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Nan-Cheng Lai , Sying-Jyan Wang , Yu-Hsuan Fu Low Power BIST with Smoother and Scan-Chain Reorder . [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Seiji Kajihara , Shin-ya Kobayashi , Yuzo Takamatsu Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Hsin-Wen Ting , Bin-Da Liu , Soon-Jyh Chang A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Guan-Xun Chen , Chung-Len Lee , Jwu E. Chen A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. [Citation Graph (0, 0)][DBLP ] Conf ] Hao-Chiao Hong , Cheng-Wen Wu , Kwang-Ting Cheng A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. [Citation Graph (0, 0)][DBLP ] Conf ] Soumendu Bhattacharya , Abhijit Chatterjee A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kohei Miyase , Seiji Kajihara , Sudhakar M. Reddy Multiple Scan Tree Design with Test Vector Modification. [Citation Graph (0, 0)][DBLP ] Conf ] Jiann-Chyi Rau , Ching-Hsiu Lin , Jun-Yi Chang An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Ming-Jing Chen , Kai-Wei Li , Yu-Liang Wu Scan-Based BIST Using an Improved Scan Forest Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Il-soo Lee , Yong Min Hur , Tony Ambler The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Hayes , Ilia Polian , Bernd Becker Testing for Missing-Gate Faults in Reversible Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Properties of Maximally Dominating Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Daisuke Yoneda , Hiroyuki Yotsuyanagi , Tetsuo Tada , Takeshi Koyama , Ikuro Morita , Takeomi Tamesada I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Rothbart , Ulrich Neffe , Christian Steger , Reinhold Weiss , Edgar Rieger , Andreas Mühlberger High Level Fault Injection for Attack Simulation in Smart Cards. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer , Sandeep K. Gupta , Shahin Nazarian Efficient Identification of Crosstalk Induced Slowdown Targets. [Citation Graph (0, 0)][DBLP ] Conf ] Wichian Sirisaengtaksin , Sandeep K. Gupta Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Chung Liang Chen , Chung-Len Lee , Ming Shae Wu A New Path Delay Test Scheme Based on Path Delay Inertia. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine Shu-Min Li , Chung-Len Lee , Chauchin Su , Jwu E. Chen A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuko Kambe , Michiko Inoue , Hideo Fujiwara Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Saeed Shamshiri , Hadi Esmaeilzadeh , Zainalabedin Navabi Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Lung Chuang , Dong-Jung Lu , Chien-Nan Jimmy Liu A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu A Systematic Way of Functional Testing for VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Chaowen Yu , Sudhakar M. Reddy , Irith Pomeranz Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Santosh Biswas , Siddhartha Mukhopadhyay , Amit Patra A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Arai , Harunobu Kurokawa , Kenichi Ichino , Satoshi Fukumoto , Kazuhiko Iwasaki Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters. [Citation Graph (0, 0)][DBLP ] Conf ] Sukanta Das , Anirban Kundu , Biplab K. Sikdar Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski Compactor Independent Direct Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] S. Ghosh , K. W. Lai , Wen-Ben Jone , Shih-Chieh Chang Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takahashi , Yukihiro Yamamoto , Yoshinobu Higami , Yuzo Takamatsu Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. [Citation Graph (0, 0)][DBLP ] Conf ] Yuichi Sato , Hiroshi Takahashi , Yoshinobu Higami , Yuzo Takamatsu Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan He , Gert Jervan , Zebo Peng , Petru Eles Hybrid BIST Test Scheduling Based on Defect Probabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Hu , Yinhe Han , Huawei Li , Tao Lv , Xiaowei Li Pair Balance-Based Test Scheduling for SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Jung-Been Im , Sunghoon Chun , Geunbae Kim , Jin-Ho Ahn , Sungho Kang RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Lun Wang March Based Memory Core Test Scheduling for SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Stina Edbom , Erik Larsson An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Tsun Huang , Jen-Chieh Yeh , Yuan-Yuan Shih , Rei-Fu Huang , Cheng-Wen Wu On Test and Diagnostics of Flash Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Simone Borri , Magali Bastian Hage-Hassan Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Ming Sheng , Ming-Jun Hsiao , Tsin-Yuan Chang A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Fu Li , Chao-Da Huang An Efficient Diagnosis Scheme for Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , John D. Reyes , Zaid Al-Ars Evaluation of Intra-Word Faults in Word-Oriented RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Rivoir Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Haur Huang , Kuen-Jong Lee , Soon-Jyh Chang A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Srinivasan , Shalabh Goyal , Abhijit Chatterjee Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] C. C. Su , C. S. Chang , H. W. Huang , D. S. Tu , C. L. Lee , Jerry C. H. Lin Dynamic Analog Testing via ATE Digital Test Channels. [Citation Graph (0, 0)][DBLP ] Conf ] Mike W. T. Wong , Yubin Zhang Design and Implementation of Self-Testable Full Range Window Comparator. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Fu Li , Chih-Chiang Hsu Efficient Test Methodologies for Conditional Sum Adders. [Citation Graph (0, 0)][DBLP ] Conf ] D. P. Vasudevan , Parag K. Lala , James Patrick Parkerson A Novel Approach for On-line Testable Reversible Logic Circuit Desig. [Citation Graph (0, 0)][DBLP ] Conf ] Sukanta Das , Biplab K. Sikdar , Parimal Pal Chaudhuri Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Guanghui Li , Xiaowei Li Circuit-Width Based Heuristic for Boolean Reasoning. [Citation Graph (0, 0)][DBLP ] Conf ] Debesh Kumar Das , Tomoo Inoue , Susanta Chakraborty , Hideo Fujiwara Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Chia Yee Ooi , Hideo Fujiwara Classification of Sequential Circuits Based on ?k Notation. [Citation Graph (0, 0)][DBLP ] Conf ] Shiy Xu , E. Edirisuriya A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey , Meng-Yao Liu Burn-In Stress Test of Analog CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Rei-Fu Huang , Chin-Lung Su , Cheng-Wen Wu , Shen-Tien Lin , Kun-Lun Luo , Yeong-Jar Chang Fail Pattern Identification for Memory Built-In Self-Repair. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Yan , Adit D. Singh Reduce Yield Loss in Delay Defect Detection in Slack Interval. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Yu Huang , Chu-Ti Lin , Chuan-Ching Sue Considering Fault Dependency and Debugging Time Lag in Reliability Growth Modeling during Software Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer Intelligible Test Techniques to Support Error-Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Min Yang , Da-Fang Zhang Bounding Rollback-Recovery of Large Distributed Computation in WAN Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan-Ching Sue , Jun-Ying Yeh , Chin-Yu Huang Full Restoration of Multiple Faults in WDM Networks without Wavelength Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Teijiro Isokawa , Nobuyuki Matsui On Improvement in Fault Tolerance of Hopfield Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Shyue-Kung Lu , Hung-Chin Wu , Shoei-Jia Yan , Yu-Cheng Tsai Testing and Diagnosis Techniques for LUT-Based FPGA's. [Citation Graph (0, 0)][DBLP ] Conf ] Donghoon Han , Abhijit Chatterjee Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Masakuni Ochi , Michihiro Shintani , Tomoo Inoue A Test Decompression Scheme for Variable-Length Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Youhua Shi , Shinji Kimura , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Wang , Sandeep K. Gupta , Melvin A. Breuer Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A Postprocessing Procedure of Test Enrichment for Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Ho Fai Ko , Nicola Nicolici Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Zenteno , Víctor H. Champac , Michel Renovell , Florence Azaïs Analysis and Attenuation Proposal in Ground Bounce. [Citation Graph (0, 0)][DBLP ] Conf ] 