Conferences in DBLP
Sudhakar M. Reddy "Challenges in Testing". [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Michael L. Bushnell , Qing Lin Redundancy Identification Using Transitive Closure. [Citation Graph (0, 0)][DBLP ] Conf ] Hsing-Chung Liang , Chung-Len Lee , Jwu E. Chen Invalid State Identification for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Stroobandt , Jan Van Campenhout Hierarchical Test Generation with Built-In Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] J. Th. van der Linden , M. H. Konijnenburg , A. J. van de Goor Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis , Rubin A. Parekhji , M. Boudjit E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Y.-M. Hur , J.-H. Shin , K.-H. Lee , Y.-S. Son , I.-C. Lim , Y.-H. Kim Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Wuudiann Ke Hybrid Pin Control Using Boundary-Scan And Its Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Hua Hong , Chung-Hung Tsai , Cheng-Wen Wu Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module. [Citation Graph (0, 0)][DBLP ] Conf ] Po-Ching Hsu , Sying-Jyan Wang Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Shyh-Shen Hwang , Shyh-Jye Jou , Yuan-Tzu Ting Syndrome Simulation And Syndrome Test For Unscanned Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Michinishi , Tokumi Yokohira , Takuji Okamoto , Tomoo Inoue , Hideo Fujiwara A Test Methodology for Interconnect Structures of LUT-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Wang-Dauh Tseng , Kuochen Wang Testable Design and Testing of MCMs Based on Multifrequency Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshihiro Konno , Kazushi Nakamura , Tatsushige Bitoh , Koji Saga , Seiken Yano A Consistent Scan Design System for Large-Scale ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Hosokawa , Kenichi Kawaguchi , Mitsuyasu Ohta , Michiaki Muraoka A Design for testability Method Using RTL Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Seiji Kajihara , Kozo Kinoshita Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Jing-Jou Tang , Tsung-Chu Huang , Cheng-Liang Tsai Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Yutaka Hata , Kazuharu Yamato On Design of Fail-Safe Cellular Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Yoon-Hwa Choi , Pong-Gyou Lee Concurrent Error Detection and Fault Location in a Fast ATM Switch. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuo Kawakubo , Koji Tanaka , Hiromi Hiraishi Formal Verification Of Self-Testing Properties Of Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yupin Luo , Shiyuan Yang , Dongcheng Hu Constructing an Edge-Route Guaranteed Optimal Fault-Tolerant Routing for Biconnected Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Inoue , Toshimitsu Masuzawa , Hiroshi Youra , Hideo Fujiwara An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuxing Zhao , Zhongcheng Li , Yinghua Min Waveform Polynomial Manipulation Using Bdds. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Ren Huang , Jing-Yang Jou , Sy-Yen Kuo , Wen-Bin Liao Easily Testable Data Path Allocation Using Input/Output Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Harry Hengster , Rolf Drechsler , Bernd Becker , Stefan Eckrich , Tonja Pfeiffer AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Sparmann , H. Mueller , Sudhakar M. Reddy Minimal Delay Test Sets for Unate Gate Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Jing-Jou Tang Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Toshimasa Kuchii , Masaki Hashizume , Takeomi Tamesada Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hisashi Kondo , Kwang-Ting Cheng An Efficient Compact Test Generator for IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , G. N. Gaydadjiev Realistic Linked Memory Cell Array Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Teruhiko Yamada , Tsuyoshi Sasaki On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng Built-In Self Test for Analog and Mixed-Signal Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Ren Huang , Jing-Yang Jou , Sy-Yen Kuo An Efficient PRPG Strategy By Utilizing Essential Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Saman Adham , Sanjay Gupta DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Bin-Hong Lin , Shao-Hui Shieh , Cheng-Wen Wu A MISR Computation Algorithm for Fast Signature Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kowen Lai , Christos A. Papachristou BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Wei , Mike W. T. Wong , Y. S. Lee Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan-Tzu Ting , Li Wei Chao , Wei Chung Chao A Practical Implementation Of Dynamic Testing Of An Ad Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher P. Fuhrman , Henri J. Nussbaumer Comparison Diagnosis in Large Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Najmi T. Jarwala , Paul W. Rutkowski , Shianling Wu , Chi W. Yau Lessons Learned from Practical Applications of BIST/B-S Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Jwu E. Chen Yield Improvement by Test Error Cancellation. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Castro Alves , A. Ribeiro Antunes , Meryem Marzouki A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Daisuke Teratani , Yoshiaki Kakuda , Tohru Kikuno A New Model with Time Constraints for Conformance Testing of Communication Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Ping Wang , Chin-Long Wey Test Generation Of Analog Switched-Current Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Székely , Márta Rencz , Jean-Michel Karam , Marcelo Lubaszewski , Bernard Courtois Thermal Monitoring Of Safety-Critical Integrated Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaofan Yang , Tinghuai Chen , Zehan Cao , Zhongshi He , Hongqing Cao A New Scheme For The Fault Diagnosis Of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Serge N. Demidenko , Vincenzo Piuri On-Line Testing In Digital Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] 