Conferences in DBLP
Vinod K. Agarwal Embedded Test and Measurement Critical for Deep Submicron Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On the Compaction of Test Sets Produced by Genetic Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Tsutomu Sasao On the Adders with Minimum Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Shinogi , Terumine Hayashi , Kazuo Taki Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. [Citation Graph (0, 0)][DBLP ] Conf ] Noriyoshi Itazaki , Yasutaka Idomoto , Kozo Kinoshita An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Silvia Chiusano , Fulvio Corno , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda Guaranteeing Testability in Re-encoding for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Perbost , Ludovic Le Lan , Christian Landrault Automatic Testability Analysis of Boards and MCMs at Chip Level. [Citation Graph (0, 0)][DBLP ] Conf ] Kwame Osei Boateng , Hiroshi Takahashi , Yuzo Takamatsu Design of C-Testable Multipliers Based on the Modified Booth Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu , Peter Waignjo , Percy G. Dias , Bole Shi Testability Prediction for Sequential Circuits Using Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda , Giovanni Squillero A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Ohtake , Tomoo Inoue , Hideo Fujiwara Sequential Test Generation Based on Circuit Pseudo-Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph C. W. Pang , Mike W. T. Wong , Y. S. Lee Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Takehiro Ito , Itsuo Takanami On fault injection approaches for fault tolerance of feedforward neural networks. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Tsunoyama , Masahiko Uenoyama , Tatsuya Kabasawa A concurrent fault-detection scheme for FFT processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hendrik Hartje , Michael Gössel , Egor S. Sogomonyan Code-Disjoint Circuits for Parity Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Junji Mori , Ben Mathew , Dave Burns , Yeuk-Hai Mok Testability Features of R10000 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Kazumi Hatayama , Mitsuji Ikeda , Masahiro Takakura , Satoshi Uchiyama , Yoriyuki Sakamoto Application of a Design for Delay Testability Approach to High Speed Logic LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Takaki Yoshida , Reisuke Shimoda , Takashi Mizokawa , Katsuhiro Hirayama An effective fault simulation method for core based LSI. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinobu Ono , Kazuo Wakui , Hitoshi Hikima , Yoshiyuki Nakamura , Masaaki Yoshida Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Michiaki Emori , Junko Kumagai , Koichi Itaya , Takashi Aikyo , Tomoko Anan , Junichi Niimi ATREX : Design for Testability System for Mega Gate LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Wen Wu On energy efficiency of VLSI testing. [Citation Graph (0, 0)][DBLP ] Conf ] Marcel Jacomet , Roger Wälti , Lukas Winzenried , Jaime Perez , Martin Gysel ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Vinay Dabholkar , Sreejit Chakravarty Computing stress tests for interconnect defects. [Citation Graph (0, 0)][DBLP ] Conf ] Josep Altet , Antonio Rubio , Hideo Tamamoto Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zahari M. Darus , Iftekhar Ahmed , Liakot Ali A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register. [Citation Graph (0, 0)][DBLP ] Conf ] Katsuyoshi Miura , Kohei Nakata , Koji Nakamae , Hiromu Fujioka Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data. [Citation Graph (0, 0)][DBLP ] Conf ] Koji Yamazaki , Teruhiko Yamada An approach to diagnose logical faults in partially observable sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Norio Kuji Guided-Probe Diagnosis of Macro-Cell-Designed LSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Naim Ben Hamida , Khaled Saab , David Marche , Bozena Kaminska A perturbation based fault modeling and simulation for mixed-signal circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi Static Testing of ADCs Using Wavelet Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Yi-Ren Cheng , Yue-Tsang Chen , Shing Tenchen Analog signal metrology for mixed signal ICs. [Citation Graph (0, 0)][DBLP ] Conf ] F. Komatsu , H. Motoki , M. Miyoshi A New Auto-Focus Method in Critical Dimension Measurement SEM. [Citation Graph (0, 0)][DBLP ] Conf ] K. Ozaki , H. Sekiguchi , S. Wakana , Y. Goto , Y. Umehara , J. Matsumoto Novel Optical Probing System for Quarter-micron VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyoshi Nikawa , Shoji Inoue New Capabilities of OBIRCH Method for Fault Localization and Defect Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Kozo Kinoshita On Acceleration of Logic Circuits Optimization Using Implication Relations. [Citation Graph (0, 0)][DBLP ] Conf ] MoonBae Song , Hoon Chang A variable reordering method for fast optimization of binary decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Yukihiro Iguchi , Tsutomu Sasao , Munehiro Matsuura On Decomposition of Kleene TDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Michinishi , Tokumi Yokohira , Takuji Okamoto , Tomoo Inoue , Hideo Fujiwara Testing for the programming circuit of LUT-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Kang Huang , M. Y. Zhang , Fred J. Meyer , Fabrizio Lombardi A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Jean Michel Portal , Joan Figueras , Yervant Zorian Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Cheer-Sun D. Yang , Lori L. Pollock An Algorithm for All-du-path Testing Coverage of Shared Memory Parallel Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Osamu Mizuno , Shinji Kusumoto , Tohru Kikuno , Yasunari Takagi , Keishi Sakamoto Estimating the Number of Faults using Simulator based on Generalized Stochastic Petri-Net Model. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Inoue , Satoshi Miyazaki , Hideo Fujiwara On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen Fault Diagnosis for Static CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chih Wei Hu , Chung-Len Lee , Wen Ching Wu , Jwu E. Chen Fault diagnosis of odd-even sorting networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Bhatia , Prab Varma Test Compaction in a Parallel Access Scan Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Hosokawa , Toshihiro Hiraoka , Mitsuyasu Ohta , Michiaki Muraoka , Shigeo Kuninobu A Partial Scan Design Method Based on n-Fold Line-up Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty On the capability of delay tests to detect bridges and opens. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takahashi , Kwame Osei Boateng , Yuzo Takamatsu , Toshiyuki Matsunaga A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wangning Long , Shiyuan Yang , Zhongcheng Li , Yinghua Min Memory Efficient ATPG for Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoming Yu , Yinghua Min Design of delay-verifiable combinational logic by adding extra inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Kowen Lai , Christos A. Papachristou , Mikhail Baklashov BIST testability enhancement using high level test synthesis for behavioral and structural designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir On Chip Weighted Random Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Yokoyama , Xiaoqing Wen , Hideo Tamamoto Random Pattern Testable Design with Partial Circuit Duplication. [Citation Graph (0, 0)][DBLP ] Conf ] Michinobu Nakao , Kazumi Hatayama , Isao Higashi Accelerated Test Points Selection Method for Scan-Based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Maneesha Dalmia , André Ivanov , Sassan Tabatabaei Power supply current monitoring techniques for testing PLLs. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Toshimasa Kuchii , Takeomi Tamesada Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Yinghua Min , Zhuxing Zhao , Zhongcheng Li IDDT Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Chu Huang , Min-Cheng Huang , Kuen-Jong Lee Built-in current sensor designs based on the bulk-driven technique. [Citation Graph (0, 0)][DBLP ] Conf ] René David Test Length for Random Testing of Sequential Machines Application to RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Yuejian Wu , Sanjay Gupta Built-In Self-Test for Multi-Port RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Gang-Min Park , Hoon Chang An extended march test algorithm for embedded memories. [Citation Graph (0, 0)][DBLP ] Conf ] Dariusz Badura , Andrzej Hlawiczka Low Cost Bist for Edac Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] 