Conferences in DBLP
T. Williams The New Frontier for Testing: Nano Meter Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir BIST Diagnostics, Part 1: Simulation Models. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Mayer , Albrecht P. Stroele Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Bechir Ayari , Prab Varma Test Cycle Count Reduction in a Parallel Scan BIST Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Castro Alves , Felipe M. G. França , Edson do Prado Granja A BIST Scheme for Asynchronous Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Paulo Sérgio Cardoso , Marius Strum , José Roberto de A. Amazonas , Wang Jiang Chau A Methodology for Minimum Area Cellular Automata Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Michiko Inoue , Takeshi Higashimura , Kenji Noda , Toshimitsu Masuzawa , Hideo Fujiwara A High-Level Synthesis Method for Weakly Testable Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Marie-Lise Flottes , R. Pires , Bruno Rouzeyre Alleviating DFT Cost Using Testability Driven HLS. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , E. Bezerra , L. Wulff , Daniel Barros Jr. Optimizing HW/SW Codesign towards Reliability for Critical-Application Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Seiji Kajihara , Kozo Kinoshita An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase Economical Importance of the Maximum Chip Area. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Wen Wu , Chih-Yuang Su A Probabilistic Model for Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Zhongcheng Li , Yinghua Min , Robert K. Brayton A New Low-Cost Method for Identifying Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Marwan A. Gharaybeh , Vishwani D. Agrawal , Michael L. Bushnell False-Path Removal Using Delay Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan-Chieh Hsu , Sandeep K. Gupta An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Huawei Li , Zhongcheng Li , Yinghua Min Delay Testing with Double Observations. [Citation Graph (0, 0)][DBLP ] Conf ] Junzhi Sang , Tsuyoshi Shinogi , Haruhiko Takase , Terumine Hayashi On a Logical Fault Model H1SGLF for Enhancing Defect Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takahashi , Kwame Osei Boateng , Yuzo Takamatsu Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Jing-Jou Tang , Wern-Yih Duh On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] S. M. Aziz , Joarder Kamruzzaman Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Haiying Tu , Fangmei Wu , Xiaoxu Ren Rough-Hierarchical Testing for Safety Critical Software. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Mouchel La Fosse A Structured Testing Approach for DSP Software. [Citation Graph (0, 0)][DBLP ] Conf ] Mukund R. Patel , Julian Fierro , Steve Pico IDDQ Test Methodology and Tradeoffs for Scan/Non-Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Tooru Honzawa , Hideo Tamamoto , Kewal K. Saluja , Kozo Kinoshita Design for Diagnosability of CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Kundu IDDQ Defect Detection in Deep Submicron CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Faust ATE Features for IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Peng-Cheng Koo , San-Liek Pang A New Technique to Ensure Quality of Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] S. R. Sabapathi Testing CPU Based Boards for Functionality Using Bus Cycle Signature System. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Devdas , André Ivanov Non-Intrusive Testing of High-Speed CML Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Terry Corpuz Fast Window Test Method of Hysteresis Test. [Citation Graph (0, 0)][DBLP ] Conf ] Kin Wee Choo , Guoxiao Guo , Ben M. Chen Development of a Multi-Channel PC-Based Hard Disk Drive Bode-Plot Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Inoue , Toshinori Hosokawa , Takahiro Mihara , Hideo Fujiwara An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Ohtake , Toshimitsu Masuzawa , Hideo Fujiwara A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] J. Th. van der Linden , M. H. Konijnenburg , A. J. van de Goor Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Teruhiko Yamada , Tsuneto Hanashima , Yasuhiro Suemori , Masaaki Maezawa On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Sumbal Rafiq , André Ivanov , Sassan Tabatabaei , Michel Renovell Testing for Floating Gates Defects in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuhiro Yanagida , Hiroshi Takahashi , Yuzo Takamatsu Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Huan Chiang , Sandeep K. Gupta BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. [Citation Graph (0, 0)][DBLP ] Conf ] Wenyi Feng , Wei-Kang Huang , Fred J. Meyer , Fabrizio Lombardi Fault Detection in a Tristate System Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Yue-Tsung Chen Comprehensive Interconnect BIST Methodology for Virtual Socket Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Jean Michel Portal , Joan Figueras , Yervant Zorian SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Noriyoshi Itazaki , Fumiro Matsuki , Yasuyuki Matsumoto , Kozo Kinoshita Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Yinlei Yu , Jian Xu , Wei-Kang Huang , Fabrizio Lombardi A Diagnosis Method for Interconnects in SRAM Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sying-Jyan Wang , Chao-Neng Huang Testing and Diagnosis of Interconnect Structures in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] J. Velasco-Medina , Marcelo Lubaszewski , Michael Nicolaidis An Approach to the On-Line Testing of Operational Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Vl. V. Saposhnikov , V. V. Saposhnikov , Alexej Dmitriev , Michael Gössel Self-Dual Duplication for Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Chun Chuang , Cheng-Wen Wu On-Line Error Detection Schemes for a Systolic Finite-Field Inverter. [Citation Graph (0, 0)][DBLP ] Conf ] Sumito Nakano , Naotake Kamiura , Yutaka Hata Fault Tolerance of a Tree-Connected Multiprocessor System and its Arraylike Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Kewal K. Saluja , Kozo Kinoshita Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Md. Altaf-Ul-Amin , Zahari Mohamed Darus An Off-Chip Current Sensor for IDDQ Testing of CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Koichi Nose , Takayasu Sakurai Integrated Current Sensing Device for Micro IDDQ Test. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Yukiya Miura , Masahiro Ichimiya , Takeomi Tamesada , Kozo Kinoshita A High-Speed IDDQ Sensor for Low-Voltage ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg E. Vollrath , Markus Huebl , Ernst Stahl Power Analysis of DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , A. J. van de Goor Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Liu , Rafic Z. Makki , Ayman I. Kayssi Dynamic Power Supply Current Testing of SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Vyacheslav N. Yarmolik , Yuri V. Klimets , Serge N. Demidenko March PS(23N) Test for DRAM Pattern-Sensitive Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Sam D. Huynh , Seongwon Kim , Mani Soma , Jinyan Zhang Dynamic Test Set Generation for Analog Circuits and Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mike W. T. Wong , Matthew Worsman DC Nonlinear Circuit Fault Simulation With Large Change Sensitivity. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Florence Azaïs , J-C. Bodin , Yves Bertrand BISTing Switched-Current Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Y.-T. Chen , C. Su Analog Module Metrology Using MNABST-1 P1149.4 Test Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Florence Azaïs , André Ivanov , Michel Renovell , Yves Bertrand A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. [Citation Graph (0, 0)][DBLP ] Conf ] Kolin Paul , A. Roy , Prasanta Kumar Nandi , B. N. Roy , M. Deb Purkayastha , Santanu Chattopadhyay , Parimal Pal Chaudhuri Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Chryssa Dislis , Gerry Musgrave , Roger B. Hughes Formal Design Techniques - Theory and Engineering Reality. [Citation Graph (0, 0)][DBLP ] Conf ] J. Gong , Eddie M. C. Wong Verification of Asynchronous Circuits with Bounded Inertial Gate Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Shing-Wu Tung , Jing-Yang Jou Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Shin'ichi Nagano , Hiroyuki Fujita , Yoshiaki Kakuda , Tohru Kikuno Application of Real-Time Temporal Logic to Design Fault Detection in Responsive Communication Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Zhen Guo , He Li , Shuling Guo , Dongsheng Wang Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Fagot , Olivier Gascuel , Patrick Girard , Christian Landrault A Ring Architecture Strategy for BIST Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaowei Li , Paul Y. S. Cheung Exploiting BIST Approach for Two-Pattern Testing. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , N. Satya Prasad Evaluating BIST Architectures for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Christian Landrault , V. Moreda , Serge Pravossoudovitch , Arnaud Virazel A BIST Structure to Test Delay Faults in a Scan Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Ismet Bayraktaroglu , K. Udawatta , Alex Orailoglu An Examination of PRPG Selection Approaches for Large, Industrial Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Hsiao , Srimat T. Chakradhar Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Surendra Bommu , Srimat T. Chakradhar , Kiran B. Doreswamy Vector Restoration Using Accelerated Validation and Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Ruifeng Guo , Irith Pomeranz , Sudhakar M. Reddy On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . [Citation Graph (0, 0)][DBLP ] Conf ] Kent L. Einspahr , Shashank K. Mehta , Sharad C. Seth Synthesis of Sequential Circuits with Clock Control to Improve Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Silvia Chiusano , Fulvio Corno , Paolo Prinetto A Test Pattern Generation Algorithm Exploiting Behavioral Information. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , W. Kent Fuchs A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination. [Citation Graph (0, 0)][DBLP ] Conf ] Madhavi Karkala , Nur A. Touba , Hans-Joachim Wunderlich Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Pingying Zeng , Zhigang Mao , Yizheng Ye , Yuliang Deng Test Pattern Generation for Column Compression Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu , Jianhua Gao An Efficient Random-like Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Hans G. Kerkhoff Microsystem Testing: Challenge or Common Knowledge?. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell Microsystems Testing: A Challenge. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Lubaszewski Bridging the Gap between Microelectronics and Micromechanics Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Wen Wu Testing Embedded Memories: Is BIST the Ultimate Solution?. [Citation Graph (0, 0)][DBLP ] Conf ] Marcel Jacomet An ASIC Designer's Point of View. [Citation Graph (0, 0)][DBLP ] Conf ] Rafic Z. Makki Testing of Embedded Memories - The Aggregate. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor Answers to the Key Issues. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Sameshima , Tomoo Fukazawa A DFT Methodology for High-Speed MCM Based on Boundary-Scan Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] 