Conferences in DBLP
Satoshi Ohtake , Michiko Inoue , Hideo Fujiwara A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase , Shinichi Yoshimura , Tomohisa Sczaki Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Atsushi Murakami , Tomohisa Kaneko On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Hiroyuki Yotsuyanagi , Takeomi Tamesada Identification of Feedback Bridging Faults with Oscillation. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , J. E. Simonse Defining SRAM Resistive Defects and Their Simulation Stimuli. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Vector-Based Functional Fault Models for Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] G. Sidiropoulos , Haridimos T. Vergos , Dimitris Nikolos Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , A. J. van de Goor March Tests for Word-Oriented Two-Port Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu , Tukwasibwe Justaf Frank An Evaluation of Test Generation Algorithms for combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zhide Zeng , Jihua Chen , Hefeng Cao Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Jou Tang An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Wenyi Feng , Wei-Kang Huang , Fred J. Meyer , Fabrizio Lombardi A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele , Frank Mayer Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Ashutosh Verma , Gaurav Chandra A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Serge N. Demidenko , Kenneth V. Lever Accelerating Test Data Processin. [Citation Graph (0, 0)][DBLP ] Conf ] Arabi Keshk , Kozo Kinoshita , Yukiya Miura Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chanyutt Arjhan , Raghvendra G. Deshmukh A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers. [Citation Graph (0, 0)][DBLP ] Conf ] Zhide Zeng , Jihua Chen , Pengxia Liu A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Yuzo Takamatsu , Kewal K. Saluja , Kozo Kinoshita Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Kozo Kinoshita , Seiji Kajihara On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase , Naoki Shindou , Kouji Akahori Scan Chain Diagnosis Using IDDQ Current Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Arabi Keshk , Kozo Kinoshita , Yukiya Miura IDDQ Current Dependency on Test Vectors and Bridging Resistance. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Shinogi , Terumine Hayashi A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hsing-Chung Liang , Chung-Len Lee An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Li Shen Genetic Algorithm Based Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mario H. Konijnenburg , Hans van der Linden , A. J. van de Goor Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Hosokawa , Toshihiro Hiraoka , Tomoo Inoue , Hideo Fujiwara Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuyuki Taniguchi , Naotake Kamiura , Yutaka Hata , Nobuyuki Matsui Activation Function Manipulation for Fault Tolerant Feedforward Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Zhang , Dongcheng Hu , Shiyuan Yang Fault-Tolerant Analysis of Feedback Neural Networks with Threshold Neurons. [Citation Graph (0, 0)][DBLP ] Conf ] Jianhua Gao , Shihuang Shao Fault-Tolerant Strategies and Their Design Methods for Application Software. [Citation Graph (0, 0)][DBLP ] Conf ] Chenglian Peng , Baifeng Wu , Xiaoguang Sun Test by Distributed Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Abdelhakim Khouas , Mohamed Dessouky , Anne Derieux Optimized Statistical Analog Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Yue-Tsang Chen , Chung-Len Lee Analog Metrology and Stimulus Selection in a Noisy Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Sam D. Huynh , Jinyan Zhang , Seongwon Kim , Giri Devarayanadurg , Mani Soma Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Fangmei Wu , Meng Li Railway Signaling Safety-critical Software Testing Based on Dynamic Decision Table. [Citation Graph (0, 0)][DBLP ] Conf ] Zhongwei Xu , Fangmei Wu A Novel Testing Approach for Safety-Critical Software. [Citation Graph (0, 0)][DBLP ] Conf ] Haiying Tu , Fangmei Wu How to Design an Environment Simulator for Safety Critical Software Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Debesh Kumar Das , Satoshi Ohtake , Hideo Fujiwara New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Teruhiko Yamada , Toshinori Kotake , Hiroshi Takahashi , Koji Yamazaki Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Jas , Kartik Mohanram , Nur A. Touba An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Youngchul Kim , C. Robert Carlson Scenario Based Integration Testing for Object-Oriented Software Development. [Citation Graph (0, 0)][DBLP ] Conf ] Huaikou Miao , Xiaolei Gao , Ling Liu An Approach to Testing the Nonexistence of Initial State in Z Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Ho , Jin-Cherng Lin Generating Test Cases for Real-Time Software by Time Petri Nets Model. [Citation Graph (0, 0)][DBLP ] Conf ] Shyue-Kung Lu , Tsung-Ying Lee , Cheng-Wen Wu Defect Level Prediction Using Multi-Model Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoya Takasaki , Hideo Fujiwara , Tomoo Inoue A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Chu Huang , Kuen-Jong Lee An Input Control Technique for Power Reduction in Scan Circuits During Test Application. [Citation Graph (0, 0)][DBLP ] Conf ] Xinghao Chen , Tom Snethen , Joe Swenton , Ron Walther A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Zulan Huang , Yizheng Ye , Zhigang Mao A New Algorithm for Retiming-Based Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Katsuyoshi Miura , Koji Nakamae , Hiromu Fujioka Intelligent EB Test System for Automatic VLSI Fault Tracing. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takahashi , Kwame Osei Boateng , Yuzo Takamatsu , Nobuhiro Yanagida Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Reisuke Shimoda , Takaki Yoshida , Masafumi Watari , Yasuhiro Toyota , Kiyokazu Nishi , Akira Motohara Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yinlei Yu , Jian Xu , Wei-Kang Huang , Fabrizio Lombardi Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Jean Michel Portal , Joan Figueras , Yervant Zorian Minimizing the Number of Test Configurations for Different FPGA Families. [Citation Graph (0, 0)][DBLP ] Conf ] Abderrahim Doumar , Hideo Ito Testing the Logic Cells and Interconnect Resources for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Lan Zhao , D. M. H. Walker , Fabrizio Lombardi IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyoshi Nikawa , Shoji Inoue , Kazuyuki Morimoto , Shinya Sone Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) Method. [Citation Graph (0, 0)][DBLP ] Conf ] Takahide Sakata , Hideyuki Takahashi , Tetsu Sekine , Toshiya Ogiwara Investigation of Ga Contamination Due to Analysis by Dual Beam FIB. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyoshi Nikawa , Shoji Inoue , Kazuyuki Morimoto , Shinya Sone Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) Method. [Citation Graph (0, 0)][DBLP ] Conf ] 