Conferences in DBLP
Vishwani D. Agrawal , Kwang-Ting Cheng Testing in the Fourth Dimension. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer , Kwang-Ting Cheng Challenges for the Academic Test Community. [Citation Graph (0, 0)][DBLP ] Conf ] Hsin-Po Wang , Jon Turino DFT and BIST techniques for the future. [Citation Graph (0, 0)][DBLP ] Conf ] F. Hayat , Thomas W. Williams , Rohit Kapur , D. Hsu DFT closure. [Citation Graph (0, 0)][DBLP ] Conf ] Wu-Tung Cheng Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey , Adam Osseiran , José Luis Huertas , Yeon-Chen Nieu Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng , Vishwani D. Agrawal , Jing-Yang Jou , Li-C. Wang , Chi-Feng Wu , Shianling Wu Collaboration between Industry and Academia in Test Research. [Citation Graph (0, 0)][DBLP ] Conf ] Sasikumar Cherubal , Abhijit Chatterjee Test generation for fault isolation in analog circuits using behavioral models. [Citation Graph (0, 0)][DBLP ] Conf ] Jun-Weir Lin , Chung-Len Lee , Chauchin Su , Jwu E. Chen Fault diagnosis for linear analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gloria Huertas , Diego Vázquez , Eduardo J. Peralías , Adoración Rueda , José L. Huertas Testing mixed-signal cores: practical oscillation-based test in an analog macrocell. [Citation Graph (0, 0)][DBLP ] Conf ] K. Y. Ko , Mike W. T. Wong New built-in self-test technique based on addition/subtraction of selected node voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wea Wang , Chi-Feng Wu , Jin-Fu Li , Cheng-Wen Wu , Tony Teng , Kevin Chiu , Hsiao-Ping Lin A built-in self-test and self-diagnosis scheme for embedded SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Reng Huang , Chee-Kian Ong , Kwang-Ting Cheng , Cheng-Wen Wu An FPGA-based re-configurable functional tester for memory chips. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Huan Chiang , Sandeep K. Gupta BIST TPG for SRAM cluster interconnect testing at board level. [Citation Graph (0, 0)][DBLP ] Conf ] Sying-Jyan Wang , Chen-Jung Wei Efficient built-in self-test algorithm for memory. [Citation Graph (0, 0)][DBLP ] Conf ] Wooyoung Choi , Ramesh Harjani , Bapiraju Vinnakota Optimal test-set generation for parametric fault detection in switched capacitor filters. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Carro , Érika F. Cota , Marcelo Lubaszewski , Yves Bertrand , Florence Azaïs , Michel Renovell TI-BIST: a temperature independent analog BIST for switched-capacitor filters. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Worsman , Mike W. T. Wong , Y. S. Lee Analog circuit equivalent faults in the D.C. domain. [Citation Graph (0, 0)][DBLP ] Conf ] Yin-Chao Huang , Chung-Len Lee , Jun-Weir Lin , Jwu E. Chen , Chauchin Su A methodology for fault model development for hierarchical linear systems. [Citation Graph (0, 0)][DBLP ] Conf ] José Vicente Calvano , Vladimir Castro Alves , Marcelo Lubaszewski Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Chi Chen , Sandeep K. Gupta , Melvin A. Breuer A new framework for static timing analysis, incremental timing refinement, and timing simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On the feasibility of fault simulation using partial circuit descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Susmita Sur-Kolay , Marly Roncken , Ken S. Stevens , Parimal Pal Chaudhuri , Rob Roy Fsimac: a fault simulator for asynchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Arabi Keshk , Yukiya Miura , Kozo Kinoshita Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislav Polonsky , Moyra K. McManus , Daniel R. Knebel , Steve Steen , Pia Sanda Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , A. J. van de Goor An experimental analysis of spot defects in SRAMs: realistic fault models and tests. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Takashi Shimono , Irith Pomeranz , Sudhakar M. Reddy Enhanced untestable path analysis using edge graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Lijian Li , Xiaoyang Yu , Cheng-Wen Wu , Yinghua Min A waveform simulator based on Boolean process. [Citation Graph (0, 0)][DBLP ] Conf ] Jennifer Dworak , Michael R. Grimaila , Brad Cobb , Ting-Chi Wang , Li-C. Wang , M. Ray Mercer On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Giani , Shuo Sheng , Michael S. Hsiao , Vishwani D. Agrawal Compaction-based test generation using state and fault information. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Yuzo Takamatsu , Kozo Kinoshita Test sequence compaction for sequential circuits with reset states. [Citation Graph (0, 0)][DBLP ] Conf ] Emil Gizdarski , Hideo Fujiwara Spirit: satisfiability problem implementation for redundancy identification and test generation. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu , Wei Cen Forecasting the efficiency of test generation algorithms for digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yiorgos Makris , Jamison Collins , Alex Orailoglu Fast hierarchical test path construction for DFT-free controller-datapath circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase , Shinichi Yoshimura Faster processing for microprocessor functional ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Hiromi Hiraishi Verification of deadlock free property of high level robot control. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Kannah , C. P. Ravikumar Functional Testing of Microprocessors with Graded Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Toshimitsu Masuzawa , Minoru Izutsu , Hiroki Wada , Hideo Fujiwara Single-control testability of RTL data paths for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] S. L. Lin , S. Mourad , S. Krishnan A BIST methodology for at-speed testing of data communications transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Der Shieh , Hsin-Fu Lo , Ming-Hwa Sheu High-speed generation of LFSR signatures. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaowei Li , Toshimitsu Masuzawa , Hideo Fujiwara Strong self-testability for data paths high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Hirayama , Jiro Okayasu , Tetsuya Yamamoto , Osamu Mizuno , Tohru Kikuno Generating test items for checking illegal behaviors in software testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Cherng Lin , Pu-Lin Yeh Using genetic algorithms for test case generation in path testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Cheng-I. Huang A hierarchical test control architecture for core based design. [Citation Graph (0, 0)][DBLP ] Conf ] Ruofan Xu , Michael S. Hsiao Embedded core testing using genetic algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Ameet Bagwe , Rubin A. Parekhji Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ding-Ming Kwai , Hung-Wen Chang , Hung-Jen Liao , Ching-Hua Chiao , Yung-Fa Chou etection of SRAM cell stability by lowering array supply voltage. [Citation Graph (0, 0)][DBLP ] Conf ] Yea-Ling Horng , Jing-Reng Huang , Tsin-Yuan Chang A realistic fault model for flash memories. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , A. J. van de Goor Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Jer Wu , Chuan Yi Tang Memory test time reduction by interconnecting test items. [Citation Graph (0, 0)][DBLP ] Conf ] Der-Cheng Huang , Wen-Ben Jone An efficient parallel transparent diagnostic BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Yu Chen , Sandeep K. Gupta , Melvin A. Breuer Test generation for crosstalk-induced faults: framework and computational result. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Liu , Fabrizio Lombardi , Wei-Kang Huang Testing programmable interconnect systems: an algorithmic approach. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Reducing test application time for full scan circuits by the addition of transfer sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Jean Michel Portal , Penelope Faure , Joan Figueras , Yervant Zorian TOF: a tool for test pattern generation optimization of an FPGA application oriented test. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Morihiro , T. Toneda Formal verification of data-path circuits based on symbolic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wen Lu , Chauchin Su , Chung-Len Lee , Jwu E. Chen Is IDDQ testing not applicable for deep submicron VLSI in year 2011? [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Hiroyuki Yotsuyanagi , Masahiro Ichimiya , Takeomi Tamesada , Masashi Takeda High speed IDDQ test and its testability for process variation. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiyuki Maeda , Kozo Kinoshita Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults. [Citation Graph (0, 0)][DBLP ] Conf ] Yann Antonioli , Tsuneo Inufushi , Shigeki Nishikawa , Kozo Kinoshita A high-speed IDDQ sensor implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Shinogi , Masahiro Ushio , Terumine Hayashi Cyclic greedy generation method for limited number of IDDQ tests. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Lun Wang , Kuen-Jong Lee Accelerated test pattern generators for mixed-mode BIST environments. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Chang , Brion L. Keller , Sarala Paliwal Effective parallel processing techniques for the generation of test data for a logic built-in self test system. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Hlawiczka , Michal Kopec Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. [Citation Graph (0, 0)][DBLP ] Conf ] Lijian Li , Yinghua Min An efficient BIST design using LFSR-ROM architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yin-He Su , Ching-Hwa Cheng , Shih-Chieh Chang Novel techniques for improving testability analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Michiko Inoue , Emil Gizdarski , Hideo Fujiwara A class of sequential circuits with combinational test generation complexity under single-fault assumption. [Citation Graph (0, 0)][DBLP ] Conf ] Marie-Lise Flottes , Christian Landrault , A. Petitqueux Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Abderrahim Doumar , Hideo Ito Testing approach within FPGA-based fault tolerant systems. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , Alexandre M. Amory Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Takashi Kodera , Nobuyuki Matsui Fault tolerant multistage interconnection networks with widely dispersed paths. [Citation Graph (0, 0)][DBLP ] Conf ] Shyue-Kung Lu , Jeh-Sheng Shih , Cheng-Wen Wu A Testable/Fault Tolerant FFT Processor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Hwa Cheng , Wen-Ben Jone , Jinn-Shyan Wang , Shih-Chieh Chang Charge sharing fault analysis and testing for CMOS domino logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Eric MacDonald , Nur A. Touba Testing domino circuits in SOI technology. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Te Kao , Sam Wu , Jwu E. Chen A case study of failure analysis and guardband determination for a 64M-bit DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Tsung-Chu Huang , Jih-Jeen Chen Peak-power reduction for multiple-scan circuits during test application. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch An adjacency-based test pattern generator for low power BIST design. [Citation Graph (0, 0)][DBLP ] Conf ] Valentin Muresan , Xiaojun Wang , Valentina Muresan , Mircea Vladutiu Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Liebelt , Cheng-Chew Lim A method for determining whether asynchronous circuits are self-checking. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir On testing safety-sensitive digital systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ismet Bayraktaroglu , Alex Orailoglu Accumulation-based concurrent fault detection for linear digital state variable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Sudhakar M. Reddy High Performance/Delay Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Tsin-Yuan Chang , Yervant Zorian SoC Testing and P1500 Standard. [Citation Graph (0, 0)][DBLP ] Conf ] 