Conferences in DBLP
Janusz Rajski DFT for High-Quality Low Cost Manufacturing Test. [Citation Graph (0, 0)][DBLP ] Conf ] Md. Altaf-Ul-Amin , Satoshi Ohtake , Hideo Fujiwara Design for Hierarchical Two-Pattern Testability of Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Yi Xu A Multiple Phase Partial Scan Design Method. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Yotsuyanagi , Shinsuke Hata , Masaki Hashizume , Takeomi Tamesada Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Klaus , A. J. van de Goor Tests for Resistive and Capacitive Defects in Address Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , A. J. van de Goor , David Eastwick , Mike Rodgers Detecting Unique Faults in Multi-port SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , A. J. van de Goor , Jens Braun , Detlev Richter A Memory Specific Notation for Fault Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz On Pass/Fail Dictionaries for Scan Circuits . [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gössel , Vitalij Ocheretnij , S. Chakrabarty Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takahashi , Marong Phadoongsidhi , Yoshinobu Higami , Kewal K. Saluja , Yuzo Takamatsu Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Naoko Takahashi , Yuzo Takamatsu Test Generation for Double Stuck-at Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Shinogi , Tomokazu Kanbayashi , Tomohiro Yoshikawa , Shinji Tsuruoka , Terumine Hayashi Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ruifeng Guo , Sudhakar M. Reddy , Irith Pomeranz On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Liang Cheng , Chia-Ming Hsueh , Jing-Reng Huang , Jen-Chieh Yeh , Chih-Tsun Huang , Cheng-Wen Wu Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Appello , Fulvio Corno , M. Giovinetto , Maurizio Rebaudengo , Matteo Sonza Reorda A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wea Wang , Ruey-Shing Tzeng , Chi-Feng Wu , Chih-Tsun Huang , Cheng-Wen Wu , Shi-Yu Huang , Shyh-Horng Lin , Hsin-Po Wang A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Teppei Takeda , Masaki Hashizume , Masahiro Ichimiya , Hiroyuki Yotsuyanagi , Yukiya Miura , Kozo Kinoshita IDDQ Sensing Technique for High Speed IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Masahiro Ichimiya , Hiroyuki Yotsuyanagi , Takeomi Tamesada CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. [Citation Graph (0, 0)][DBLP ] Conf ] Iwao Yamazaki , Hiroki Yamanaka , Toshio Ikeda , Masahiro Takakura , Yasuo Sato An Approach to Improve the Resolution of Defect-Based Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kwame Osei Boateng , Hideaki Konishi , Tsuneo Nakata A Method of Static Compaction of Test Stimuli. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Atsuhiro Ogawa , Tomoo Inoue , Akio Tamura Dynamic Test Compression Using Statistical Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Mill-Jer Wang , R.-L. Jiang , J.-W. Hsia , Chih-Hu Wang , Jwu E. Chen Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Stefano Di Carlo , Giorgio Di Natale , Paolo Prinetto Memory Read Faults: Taxonomy and Automatic Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Serge N. Demidenko , A. J. van de Goor , S. Henderson , P. Knoppers Simulation and Development of Short Transparent Tests for RAM. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Norio Kuji , Takako Ishihara EB-Testing-Pad Method and Its Evaluation by Actual Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey A. Block , William K. Lo , Chris Shaw Benefits of Phase Interference Detection to IC Waveform Probing. [Citation Graph (0, 0)][DBLP ] Conf ] Tomokazu Yoneda , Hideo Fujiwara A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu Compaction Schemes with Minimum Test Application Time. [Citation Graph (0, 0)][DBLP ] Conf ] Zahra Sadat Ebadi , André Ivanov Design of an Optimal Test Access Architecture Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Huawei Li , Yinghua Min , Zhongcheng Li An RT-Level ATPG Based on Clustering of Circuit States. [Citation Graph (0, 0)][DBLP ] Conf ] Zhigang Yin , Yinghua Min , Xiaowei Li An Approach to RTL Fault Extraction and Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Gianluca Cumani , Matteo Sonza Reorda , Giovanni Squillero Effective Techniques for High-Level ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Yun Shao , Sudhakar M. Reddy , Seiji Kajihara , Irith Pomeranz An Efficient Method to Identify Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Kee Sup Kim , Rathish Jayabharathi , Craig Carstens SpeedGrade: An RTL Path Delay Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Michinobu Nakao , Yoshikazu Kiyoshige , Kazumi Hatayama , Yasuo Sato , Takaharu Nagumo Test Generation for Multiple-Threshold Gate-Delay Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick Bonhomme , Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Larsson , Zebo Peng Test Scheduling and Scan-Chain Division under Power Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Wu-Tung Cheng , Chien-Chung Tsai , Nilanjan Mukherjee , Omer Samman , Yahya Zaidan , Sudhakar M. Reddy Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. [Citation Graph (0, 0)][DBLP ] Conf ] Parag K. Lala , Alvernon Walker A Unified Scheme for Designing Testable State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Samrat Goswami , Anupam Chanda , D. Roy Choudhury Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Biplab K. Sikdar , Samir Roy , Debesh K. Das Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanuel Simeu , Ahmad Abdelhay , Mohammad A. Naal Robust Self Concurrent Test of Linear Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Stefano Di Carlo , Giorgio Di Natale , Paolo Prinetto , Luca Tagliaferri Control-Flow Checking via Regular Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Pierluigi Civera , Luca Macchiarulo , Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante FPGA-Based Fault Injection for Microprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ken-ichi Yamaguchi , Hiroki Wada , Toshimitsu Masuzawa , Hideo Fujiwara BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Sobeeh Almukhaizim , Peter Petrov , Alex Orailoglu Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Könemann , Carl Barnhart , Brion L. Keller , Tom Snethen , Owen Farnsworth , Donald L. Wheater A SmartBIST Variant with Guaranteed Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshikazu Takahashi MEMS Comb-Actuator Resonance Measurement Method Using the 2nd Harmonics of the GND Current. [Citation Graph (0, 0)][DBLP ] Conf ] Zhen Guo , Xi Min Zhang , Jacob Savir , Yun-Qing Shi On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Achintya Halder , Abhijit Chatterjee Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase Yield Increase of VLSI after Redundancy-Repairing. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Yasuyuki Taniguchi , Teijiro Isokawa , Nobuyuki Matsui An Improvement in Weight-Fault Tolerance of Feedforward Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Vitalij Ocheretnij , Egor S. Sogomonyan , Michael Gössel A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Ismet Bayraktaroglu , Alex Orailoglu Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? [Citation Graph (0, 0)][DBLP ] Conf ] Kenichi Ichino , Takeshi Asakawa , Satoshi Fukumoto , Kazuhiko Iwasaki , Seiji Kajihara Hybrid BIST Using Partially Rotational Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Biplab K. Sikdar , Niloy Ganguly , Aniket Karmakar , Subha Sankar Chowdhury , Parimal Pal Chaudhuri Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dongkyu Youn , Taehyung Kim , Sungju Park A Microcode-Based Memory BIST Implementing Modified March Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Hamed Farshbaf , Mina Zolfy , Shahrzad Mirkhani , Zainalabedin Navabi Fault Simulation for VHDL Based Test Bench and BIST Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Biranchinath Sahu , Abhijit Chatterjee Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred V. Gomes , Abhijit Chatterjee Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator. [Citation Graph (0, 0)][DBLP ] Conf ] A. Lechner , A. Richardson , B. Hermes Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft? [Citation Graph (0, 0)][DBLP ] Conf ] Jeng-Horng Tsai , Ming-Jun Hsiao , Tsin-Yuan Chang An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Yao Wang , Shing-Wu Tung , Jing-Yang Jou An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Zhou , Tomohiro Yoneda , Chris J. Myers Framework of Timed Trace Theoretic Verification Revisited. [Citation Graph (0, 0)][DBLP ] Conf ] Ilia Polian , Wolfgang Günther , Bernd Becker Efficient Pattern-Based Verification of Connections to IP Cores . [Citation Graph (0, 0)][DBLP ] Conf ] Bipul Chandra Paul , Seung Hoon Choi , Yonghee Im , Kaushik Roy Design Verification and Robust Design Technique for Cross-Talk Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuo Sato , M. Sato , K. Tsutsumida , Toyohito Ikeya , M. Kawashima A Practical Logic BIST for ASIC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuo Kamada Tx7901 Dft. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinobu Ono , Akira Kozawa , Takashi Kimura , Yoshihiro Konno , Koji Saga An Application of Partial Scan Techniques to a High-End System LSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Hisayoshi Hanai , Shinji Yamada , Hisaya Mori , Eisaku Yamashita , Teruhiko Funakura Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs. [Citation Graph (0, 0)][DBLP ] Conf ] M. Suzuki , R. Shimizu , N. Naka , K. Nakamura High-Speed Interface Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuji Kishi , Mitsuyasu Ohta , Takashi Taniguchi , Hiroshi Kadota A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Hsin-Po Wang A Flexible Logic BIST Scheme and Its Application to SoC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy , Xijiang Lin Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu Non-exhaustive Parity Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuya Shimizu , Noriyoshi Itazaki , Kozo Kinoshita Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Chu Huang , Kuen-Jong Lee A Low-Power LFSR Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] 