Conferences in DBLP
Kewal K. Saluja Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian Leveraging Infrastructure IP for SoC Yield. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Yotsuyanagi , Toshimasa Kuchii , Shigeki Nishikawa , Masaki Hashizume , Kozo Kinoshita Reducing Scan Shifts Using Folding Scan Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Ming-Jing Chen , Jia-Guang Sun , Hideo Fujiwara Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Xiangdong Xuan , Abhijit Chatterjee , Adit D. Singh , Namsoo P. Kim , Mark T. Chisa IC Reliability Simulator ARET and Its Application in Design-for-Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , A. J. van de Goor Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. [Citation Graph (0, 0)][DBLP ] Conf ] Yuki Yamagata , Kenichi Ichino , Masayuki Arai , Satoshi Fukumoto , Kazuhiko Iwasaki , Masayuki Satoh , Hiroyuki Itabashi , Takashi Murai , Nobuyuki Otsuka Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrizio Bertuccelli , Franco Bigongiari , Andrea S. Brogna , Giorgio Di Natale , Paolo Prinetto , Roberto Saletti Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Chiun Lin , Shi-Yu Huang Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Wu-Tung Cheng , Cheng-Ju Hsieh , Huan-Yung Tseng , Alou Huang , Yu-Ting Hung Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaofan Yang A Linear Time Fault Diagnosis Algorithm for Hypercube Multiprocessors under the MM* Comparison Model. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Iwagaki , Satoshi Ohtake , Hideo Fujiwara Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. [Citation Graph (0, 0)][DBLP ] Conf ] Masayasu Fukunaga , Seiji Kajihara , Sadami Takeoka On Estimation of Fault Efficiency for Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Virendra Singh , Michiko Inoue , Kewal K. Saluja , Hideo Fujiwara Software-Based Delay Fault Testing of Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A DFT Approach for Path Delay Faults in Interconnected Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sukanta Das , Anirban Kundu , Subhayan Sen , Biplab K. Sikdar , Parimal Pal Chaudhuri Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Ehsan Atoofian , Zainalabedin Navabi A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. [Citation Graph (0, 0)][DBLP ] Conf ] Md. Rafiqul Islam , Hafiz Md. Hasan Babu , Mohammad Abdur Rahim Mustafa , Md. Sumon Shahriar A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Ruilian Zhao , Michael R. Lyu , Yinghua Min Domain Testing Based on Character String Predicate. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Beyer , Winfried Dulz , Fenhua Zhen Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Fangmei Wu , Lei Huang Efficiency Analysis and Safety Assessment of Automatic Testing for Safety-Critical Software. [Citation Graph (0, 0)][DBLP ] Conf ] Yunzhan Gong , Wanli Xu , Xiaowei Li An Expression's Single Fault Model and the Testing Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Jayasanker Jayabalan , Chee Kiang Goh , Ooi Ban Leong , Leong Mook Seng , Mahadevan K. Iyer , Andrew A. O. Tay PLL Based High Speed Functional Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Mike W. T. Wong Issues Related to the Formulation of DFT Solution for Analog Circuit Test Using Equivalent Fault Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Soon-Jyh Chang , Ruei-Shiuan Tzeng A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Hosokawa , Hiroshi Date , Masahide Miyazaki , Michiaki Muraoka , Hideo Fujiwara A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Kohei Miyase , Seiji Kajihara Optimal Scan Tree Construction with Test Vector Modification for Test Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Koenemann STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Zhang , Michael S. Hsiao , Indradeep Ghosh Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Tun Li , Yang Guo , Sikun Li An Automatic Circuit Extractor for RTL Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Lv , Jianping Fan , Xiaowei Li An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Jean Marc Galliere , Florence Azaïs , Yves Bertrand Delay Testing of MOS Transistor with Gate Oxide Short. [Citation Graph (0, 0)][DBLP ] Conf ] Arani Sinha , Sandeep K. Gupta , Melvin A. Breuer An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Huawei Li , Yue Zhang , Xiaowei Li Delay Test Pattern Generation Considering Crosstalk-Induced Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir , Jing Zeng , Carol Pyron , Juhong Zhu Automated Test Model Generation from Switch Level Custom Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Samir Roy , Biplab K. Sikdar Power Conscious BIST Design for Sequential Circuits Using ghost-FSM. [Citation Graph (0, 0)][DBLP ] Conf ] Yongjun Xu , Zuying Luo , Zhiguo Chen , Xiaowei Li Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Hirayama , Tetsuya Yamamoto , Osamu Mizuno , Tohru Kikuno Analysis of Software Test Item Generation - Comparison between High Skilled and Low Skilled Engineers. [Citation Graph (0, 0)][DBLP ] Conf ] Chang Xu , Beihong Jin Conformance Test of Distributed Transaction Service. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu Build-In-Self-Test for Software. [Citation Graph (0, 0)][DBLP ] Conf ] Hui-Qun Zhao , Qin-Xin Gao , Yuan Gao Testing the Conformity of Transactional Attributes of Components by Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Baris Arslan , Alex Orailoglu Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Hideo Tamamoto , Kewal K. Saluja , Kozo Kinoshita Fault Diagnosis for Physical Defects of Unknown Behaviors. [Citation Graph (0, 0)][DBLP ] Conf ] Pan Zhongliang Fault Detection for Testable Realizations of Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Simone Borri Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Rei-Fu Huang , Yung-Fa Chou , Cheng-Wen Wu Defect Oriented Fault Analysis for SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] L. Kalyan Kumar , Amol J. Mupid , Aditya S. Ramani , V. Kamakoti A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Shinogi , Yuki Yamada , Terumine Hayashi , Tomohiro Yoshikawa , Shinji Tsuruoka Between-Core Vector Overlapping for Test Cost Reduction in Core Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Pedram A. Riahi , Zainalabedin Navabi , Fabrizio Lombardi The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Zhigang Jiang , Sandeep K. Gupta A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Hafizur Rahaman , Debesh K. Das , Bhargab B. Bhattacharya Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Junhao Shi , Görschwin Fey , Rolf Drechsler BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Michiko Inoue , Kazuhiro Suzuki , Hiroyuki Okamoto , Hideo Fujiwara Test Synthesis for Datapaths Using Datapath-Controller Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Shan Gu , Hideo Fujiwara Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Larsson , Hideo Fujiwara Optimal System-on-Chip Test Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Julien Pouget , Erik Larsson , Zebo Peng SOC Test Time Minimization Under Multiple Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Jervan , Petru Eles , Zebo Peng , Raimund Ubar , Maksim Jenihhin Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tian Xia , Jien-Chung Lo On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Cheng Tsai , Chung-Len Lee An On-Chip Jitter Measurement Circuit for the PLL. [Citation Graph (0, 0)][DBLP ] Conf ] Jui-Jer Huang , Jiun-Lang Huang A Low-Cost Jitter Measurement Technique for BIST Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Junfeng Wang , Jianhua Yang , Gaogang Xie , Mingtian Zhou , Zhongcheng Li Measurement-Based Modeling with Adaptive Sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Baosheng Wang , Yong B. Cho , Sassan Tabatabaei , André Ivanov Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yuxin Tian , Michael R. Grimaila , Weiping Shi , M. Ray Mercer Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Rivoir Lowering Cost of Test: Parallel Test or Low-Cost ATE? [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Lung Su , Rei-Fu Huang , Cheng-Wen Wu A Processor-Based Built-In Self-Repair Design for Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , Zaid Al-Ars , A. J. van de Goor , Mike Rodgers March SL: A Test For All Static Linked Memory Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaogang Du , Sudhakar M. Reddy , Joseph Rayhawk , Wu-Tung Cheng Testing Delay Faults in Embedded CAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Gh. Mohammad , Kewal K. Saluja Stress Test for Disturb Faults in Non-Volatile Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Teppei Takeda , Hiroyuki Yotsuyanagi , Takeomi Tamesada , Yukiya Miura , Kozo Kinoshita A BIST Circuit for IDDQ Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Yinghua Min , Jishun Kuang , Xiaoyan Niu At-Speed Current Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jishun Kuang , Yu Wang , Xiaofen Wei , Changnian Zhang IDDT ATPG Based on Ambiguous Delay Assignments. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Michinishi , Tokumi Yokohira , Takuji Okamoto , Toshifumi Kobayashi , Tsutomu Hondo Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test. [Citation Graph (0, 0)][DBLP ] Conf ] Masahide Miyazaki , Toshinori Hosokawa , Hiroshi Date , Michiaki Muraoka , Hideo Fujiwara A DFT Selection Method for Reducing Test Application Time of System-on-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Huaguo Liang , Cuiyun Jiang Sharing BIST with Multiple Cores for System-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Md. Saffat Quasem , Sandeep K. Gupta Designing Multiple Scan Chains for Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Yingxiang Wang , Weikang Huang Optimizing Test Access Mechanism under Constraints by Genetic Local Search Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Test Data Volume Reduction by Test Data Realignment. [Citation Graph (0, 0)][DBLP ] Conf ] Yinhe Han , Yongjun Xu , Huawei Li , Xiaowei Li , Anshuman Chandra Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Michihiro Shintani , Toshihiro Ohara , Tomoo Inoue Test Response Compression Based on Huffman Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Gaocai Wang , Jianer Chen , Guojun Wang , Songqiao Chen Probability Model for Faults in Large-Scale Multicomputer Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ling Liu , Wennan Feng , Song Jia , Anping Jiang , Lijiu Ji Design Retargetable Platform System for Microprocessor Functional Test. [Citation Graph (0, 0)][DBLP ] Conf ] Piotr Gawkowski , Janusz Sosnowski Assessing Software Implemented Fault Detection and Fault Tolerance Mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , Rubem Dutra R. Fagundes , Daniel Barros Jr. , Diogo B. Brum Briefing a New Approach to Improve the EMI Immunity of DSP Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Guanghui Li , Ming Shao , Xiaowei Li Design Error Diagnosis Based on Verification Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Shao , Guanghui Li , Xiaowei Li SAT-Based Algorithm of Verification for Port Order Fault. [Citation Graph (0, 0)][DBLP ] Conf ] Zhan Xu , Xiaolang Yan , Yongjiang Lu , Haitong Ge Equivalence Checking Using Independent Cuts. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Zhu , Jianhua Gao A Method to Calculate the Reliability of Component-Based Software. [Citation Graph (0, 0)][DBLP ] Conf ] Da-Hai Jin , Yun-Zhan Gong An Object-Oriented Program Automatic Execute Model and the Research of Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Min Yang , Da-Fang Zhang , Xue Dong Yang User-Level Implementation of Checkpointing for Multithreaded Applications on Windows NT. [Citation Graph (0, 0)][DBLP ] Conf ] Li Shen RTL Concurrent Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Zhu , Jinian Bian , Weimin Wu , Hongxi Xue Property Classification for Functional Verification Based. [Citation Graph (0, 0)][DBLP ] Conf ] Jian-Hui Jiang Error Detection and Correction in VLSI Systems by Online Testing and Retrying. [Citation Graph (0, 0)][DBLP ] Conf ] Saeed Safari , Hadi Esmaeilzadeh , Amir-Hossein Jahangir Testability Improvement During High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Yong-sheng Wang , Liyi Xiao , Mingyan Yu , Jin-xiang Wang , Yizheng Ye A Test Architecture for System-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] He Hu , Yihe Sun Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase Test Pattern Length Required to Reach the Desired Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Zhongwei Xu , Bangxing Chen Damage Size and Software Safety Demonstration Stress Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Meng Li , Zhu Xu Study on the Cost/Benefit/Optimization of Software Safety Test. [Citation Graph (0, 0)][DBLP ] Conf ] 