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Asian Test Symposium (ats)
2003 (conf/ats/2003)

  1. Kewal K. Saluja
    Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:2- [Conf]
  2. Yervant Zorian
    Leveraging Infrastructure IP for SoC Yield. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:3-5 [Conf]
  3. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
    Reducing Scan Shifts Using Folding Scan Trees. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:6-11 [Conf]
  4. Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara
    Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:12-17 [Conf]
  5. Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa
    IC Reliability Simulator ARET and Its Application in Design-for-Reliability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:18-23 [Conf]
  6. Zaid Al-Ars, A. J. van de Goor
    Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:24-27 [Conf]
  7. Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka
    Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:28-31 [Conf]
  8. Fabrizio Bertuccelli, Franco Bigongiari, Andrea S. Brogna, Giorgio Di Natale, Paolo Prinetto, Roberto Saletti
    Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:32-37 [Conf]
  9. Yu-Chiun Lin, Shi-Yu Huang
    Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:38-43 [Conf]
  10. Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
    Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:44-49 [Conf]
  11. Xiaofan Yang
    A Linear Time Fault Diagnosis Algorithm for Hypercube Multiprocessors under the MM* Comparison Model. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:50-57 [Conf]
  12. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
    Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:58-63 [Conf]
  13. Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka
    On Estimation of Fault Efficiency for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:64-67 [Conf]
  14. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Software-Based Delay Fault Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:68-71 [Conf]
  15. Irith Pomeranz, Sudhakar M. Reddy
    A DFT Approach for Path Delay Faults in Interconnected Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:72-77 [Conf]
  16. Sukanta Das, Anirban Kundu, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:78-83 [Conf]
  17. Ehsan Atoofian, Zainalabedin Navabi
    A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:84-89 [Conf]
  18. Md. Rafiqul Islam, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar
    A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:90-95 [Conf]
  19. Ruilian Zhao, Michael R. Lyu, Yinghua Min
    Domain Testing Based on Character String Predicate. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:96-101 [Conf]
  20. Matthias Beyer, Winfried Dulz, Fenhua Zhen
    Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov Chains. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:102-105 [Conf]
  21. Fangmei Wu, Lei Huang
    Efficiency Analysis and Safety Assessment of Automatic Testing for Safety-Critical Software. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:106-109 [Conf]
  22. Yunzhan Gong, Wanli Xu, Xiaowei Li
    An Expression's Single Fault Model and the Testing Methods. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:110-115 [Conf]
  23. Jayasanker Jayabalan, Chee Kiang Goh, Ooi Ban Leong, Leong Mook Seng, Mahadevan K. Iyer, Andrew A. O. Tay
    PLL Based High Speed Functional Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:116-119 [Conf]
  24. Mike W. T. Wong
    Issues Related to the Formulation of DFT Solution for Analog Circuit Test Using Equivalent Fault Analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:120-123 [Conf]
  25. Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng
    A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:124-129 [Conf]
  26. Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
    A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:130-135 [Conf]
  27. Kohei Miyase, Seiji Kajihara
    Optimal Scan Tree Construction with Test Vector Modification for Test Compression. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:136-141 [Conf]
  28. Bernd Koenemann
    STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:142-147 [Conf]
  29. Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
    Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:148-153 [Conf]
  30. Tun Li, Yang Guo, Sikun Li
    An Automatic Circuit Extractor for RTL Verification. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:154-160 [Conf]
  31. Tao Lv, Jianping Fan, Xiaowei Li
    An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:161-167 [Conf]
  32. Michel Renovell, Jean Marc Galliere, Florence Azaïs, Yves Bertrand
    Delay Testing of MOS Transistor with Gate Oxide Short. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:168-173 [Conf]
  33. Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
    An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:174-177 [Conf]
  34. Huawei Li, Yue Zhang, Xiaowei Li
    Delay Test Pattern Generation Considering Crosstalk-Induced Effects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:178-183 [Conf]
  35. Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu
    Automated Test Model Generation from Switch Level Custom Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:184-189 [Conf]
  36. Samir Roy, Biplab K. Sikdar
    Power Conscious BIST Design for Sequential Circuits Using ghost-FSM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:190-195 [Conf]
  37. Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li
    Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:196-201 [Conf]
  38. Ozgur Sinanoglu, Alex Orailoglu
    Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:202-209 [Conf]
  39. Masayuki Hirayama, Tetsuya Yamamoto, Osamu Mizuno, Tohru Kikuno
    Analysis of Software Test Item Generation - Comparison between High Skilled and Low Skilled Engineers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:210-215 [Conf]
  40. Chang Xu, Beihong Jin
    Conformance Test of Distributed Transaction Service. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:216-219 [Conf]
  41. Shiyi Xu
    Build-In-Self-Test for Software. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:220-223 [Conf]
  42. Hui-Qun Zhao, Qin-Xin Gao, Yuan Gao
    Testing the Conformity of Transactional Attributes of Components by Simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:224-229 [Conf]
  43. Baris Arslan, Alex Orailoglu
    Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:230-235 [Conf]
  44. Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
    Fault Diagnosis for Physical Defects of Unknown Behaviors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:236-241 [Conf]
  45. Pan Zhongliang
    Fault Detection for Testable Realizations of Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:242-249 [Conf]
  46. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
    Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:250-255 [Conf]
  47. Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu
    Defect Oriented Fault Analysis for SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:256-261 [Conf]
  48. L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
    A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:262-267 [Conf]
  49. Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka
    Between-Core Vector Overlapping for Test Cost Reduction in Core Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:268-273 [Conf]
  50. Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi
    The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:274-277 [Conf]
  51. Zhigang Jiang, Sandeep K. Gupta
    A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:278-283 [Conf]
  52. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:284-289 [Conf]
  53. Junhao Shi, Görschwin Fey, Rolf Drechsler
    BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:290-293 [Conf]
  54. Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara
    Test Synthesis for Datapaths Using Datapath-Controller Functions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:294-299 [Conf]
  55. Dong Xiang, Shan Gu, Hideo Fujiwara
    Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:300-305 [Conf]
  56. Erik Larsson, Hideo Fujiwara
    Optimal System-on-Chip Test Scheduling. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:306-311 [Conf]
  57. Julien Pouget, Erik Larsson, Zebo Peng
    SOC Test Time Minimization Under Multiple Constraints. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:312-317 [Conf]
  58. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:318-325 [Conf]
  59. Tian Xia, Jien-Chung Lo
    On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:326-331 [Conf]
  60. Chin-Cheng Tsai, Chung-Len Lee
    An On-Chip Jitter Measurement Circuit for the PLL. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:332-335 [Conf]
  61. Jui-Jer Huang, Jiun-Lang Huang
    A Low-Cost Jitter Measurement Technique for BIST Applications. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:336-339 [Conf]
  62. Junfeng Wang, Jianhua Yang, Gaogang Xie, Mingtian Zhou, Zhongcheng Li
    Measurement-Based Modeling with Adaptive Sampling. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:340-347 [Conf]
  63. Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov
    Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:348-353 [Conf]
  64. Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
    Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:354-359 [Conf]
  65. Jochen Rivoir
    Lowering Cost of Test: Parallel Test or Low-Cost ATE? [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:360-365 [Conf]
  66. Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu
    A Processor-Based Built-In Self-Repair Design for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:366-371 [Conf]
  67. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers
    March SL: A Test For All Static Linked Memory Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:372-377 [Conf]
  68. Xiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng
    Testing Delay Faults in Embedded CAMs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:378-383 [Conf]
  69. Mohammad Gh. Mohammad, Kewal K. Saluja
    Stress Test for Disturb Faults in Non-Volatile Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:384-389 [Conf]
  70. Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
    A BIST Circuit for IDDQ Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:390-395 [Conf]
  71. Yinghua Min, Jishun Kuang, Xiaoyan Niu
    At-Speed Current Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:396-399 [Conf]
  72. Jishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang
    IDDT ATPG Based on Ambiguous Delay Assignments. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:400-405 [Conf]
  73. Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo
    Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:406-411 [Conf]
  74. Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
    A DFT Selection Method for Reducing Test Application Time of System-on-Chips. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:412-417 [Conf]
  75. Huaguo Liang, Cuiyun Jiang
    Sharing BIST with Multiple Cores for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:418-423 [Conf]
  76. Md. Saffat Quasem, Sandeep K. Gupta
    Designing Multiple Scan Chains for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:424-427 [Conf]
  77. Yingxiang Wang, Weikang Huang
    Optimizing Test Access Mechanism under Constraints by Genetic Local Search Algorithm. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:428-433 [Conf]
  78. Irith Pomeranz, Sudhakar M. Reddy
    Test Data Volume Reduction by Test Data Realignment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:434-439 [Conf]
  79. Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:440-445 [Conf]
  80. Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue
    Test Response Compression Based on Huffman Coding. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:446-451 [Conf]
  81. Gaocai Wang, Jianer Chen, Guojun Wang, Songqiao Chen
    Probability Model for Faults in Large-Scale Multicomputer Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:452-457 [Conf]
  82. Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji
    Design Retargetable Platform System for Microprocessor Functional Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:458-461 [Conf]
  83. Piotr Gawkowski, Janusz Sosnowski
    Assessing Software Implemented Fault Detection and Fault Tolerance Mechanisms. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:462-467 [Conf]
  84. Fabian Vargas, Rubem Dutra R. Fagundes, Daniel Barros Jr., Diogo B. Brum
    Briefing a New Approach to Improve the EMI Immunity of DSP Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:468-473 [Conf]
  85. Guanghui Li, Ming Shao, Xiaowei Li
    Design Error Diagnosis Based on Verification Techniques. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:474-477 [Conf]
  86. Ming Shao, Guanghui Li, Xiaowei Li
    SAT-Based Algorithm of Verification for Port Order Fault. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:478-481 [Conf]
  87. Zhan Xu, Xiaolang Yan, Yongjiang Lu, Haitong Ge
    Equivalence Checking Using Independent Cuts. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:482-487 [Conf]
  88. Yuan Zhu, Jianhua Gao
    A Method to Calculate the Reliability of Component-Based Software. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:488-491 [Conf]
  89. Da-Hai Jin, Yun-Zhan Gong
    An Object-Oriented Program Automatic Execute Model and the Research of Algorithm. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:492-495 [Conf]
  90. Jin-Min Yang, Da-Fang Zhang, Xue Dong Yang
    User-Level Implementation of Checkpointing for Multithreaded Applications on Windows NT. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:496-501 [Conf]
  91. Li Shen
    RTL Concurrent Fault Simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:502- [Conf]
  92. Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue
    Property Classification for Functional Verification Based. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:503- [Conf]
  93. Jian-Hui Jiang
    Error Detection and Correction in VLSI Systems by Online Testing and Retrying. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:504- [Conf]
  94. Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir
    Testability Improvement During High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:505- [Conf]
  95. Yong-sheng Wang, Liyi Xiao, Mingyan Yu, Jin-xiang Wang, Yizheng Ye
    A Test Architecture for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:506- [Conf]
  96. He Hu, Yihe Sun
    Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:507- [Conf]
  97. Junichi Hirase
    Test Pattern Length Required to Reach the Desired Fault Coverage. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:508- [Conf]
  98. Zhongwei Xu, Bangxing Chen
    Damage Size and Software Safety Demonstration Stress Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:509- [Conf]
  99. Meng Li, Zhu Xu
    Study on the Cost/Benefit/Optimization of Software Safety Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:510- [Conf]
NOTICE1
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
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