Conferences in DBLP
Rajeev Alur Games for Formal Design and Verification of Reactive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Kurshan Evolution of Model Checking into the EDA Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Pei-Hsin Ho Abstraction Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Tevfik Bultan , Xiang Fu , Jianwen Su Tools for Automated Verification of Web Services. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Pierre Jouannaud Theorem Proving Languages for Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoying Liu An Automated Rigorous Review Method for Verifying and Validating Formal Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Fang Yu , Bow-Yaw Wang Toward Unbounded Model Checking for Region Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Bai Su , Wenhui Zhang Search Space Partition and Case Basis Exploration for Reducing Model Checking Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] David Sinclair , David Gray , Geoff Hamilton Synthesising Attacks on Cryptographic Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Ehud Friedgut , Orna Kupferman , Moshe Y. Vardi Büchi Complementation Made Tighter. [Citation Graph (0, 0)][DBLP ] Conf ] Shougo Ogata , Tatsuhiro Tsuchiya , Tohru Kikuno SAT-Based Verification of Safe Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Jérôme Leroux Disjunctive Invariants for Numerical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Moritomo , Kiyoharu Hamaguchi , Toshinobu Kashiwabara Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas. [Citation Graph (0, 0)][DBLP ] Conf ] Robi Malik , David Streader , Steve Reeves Fair Testing Revisited: A Process-Algebraic Characterisation of Conflicts. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Cibrario Bertolotti , Luca Durante , Riccardo Sisto , Adriano Valenzano Exploiting Symmetries for Testing Equivalence in the Spi Calculus. [Citation Graph (0, 0)][DBLP ] Conf ] Cyrille Artho , Klaus Havelund , Armin Biere Using Block-Local Atomicity to Detect Stale-Value Concurrency Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Kairong Qian , Albert Nymeyer Abstraction-Based Model Checking Using Heuristical Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Tadaaki Tanimoto , Suguru Sasaki , Akio Nakata , Teruo Higashino A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Serge Haddad , Jean-Michel Ilié , Kais Klai Design and Evaluation of a Symbolic and Abstraction-Based Model Checker. [Citation Graph (0, 0)][DBLP ] Conf ] Abdur Rakib , Oleg Parshin , Stephan Thesing , Reinhard Wilhelm Component-Wise Instruction-Cache Behavior Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] I. Gordin , Raya Leviathan , Amir Pnueli Validating the Translation of an Industrial Optimizing Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Sébastien Bardin , Alain Finkel Composition of Accelerations to Verify Infinite Heterogeneous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ansgar Fehnker , Bruce H. Krogh Hybrid System Verification Is Not a Sinecure: The Electronic Throttle Control Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Tarek Mhamdi , Sofiène Tahar Providing Automated Verification in HOL Using MDGs. [Citation Graph (0, 0)][DBLP ] Conf ] Konstantine Arkoudas Specification, Abduction, and Proof. [Citation Graph (0, 0)][DBLP ] Conf ] Marisa Llorens , Javier Oliver Introducing Structural Dynamic Changes in Petri Nets: Marked-Controlled Reconfigurable Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Orna Kupferman , Gila Morgenstern , Aniello Murano Typeness for omega-Regular Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Denduang Pradubsuwun , Tomohiro Yoneda , Chris J. Myers Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Te-Chang Lee , Pao-Ann Hsiung Mutation Coverage Estimation for Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Claudio de la Riva , Javier Tuya Modular Model Checking of Software Specifications with Simultaneous Environment Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Kikuchi Rabin Tree and Its Application to Group Key Distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Mark J. Karol , P. Krishnan , J. Jenny Li Using Overlay Networks to Improve VoIP Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Kui Chang , Chun-Yuan Chen Integrity-Enhanced Verification Scheme for Software-Intensive Organizations. [Citation Graph (0, 0)][DBLP ] Conf ] Trong-Yen Lee , Yang-Hsin Fan , Tsung-Hsun Yang , Chia-Chun Tsai , Wen-Ta Lee , Yuh-Shyan Hwang RCGES: Retargetable Code Generation for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Little , David Walter , Nicholas Seegmiller , Chris J. Myers , Tomohiro Yoneda Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Fang Wang , Sofiène Tahar , Otmane Aït Mohamed First-Order LTL Model Checking Using MDGs. [Citation Graph (0, 0)][DBLP ] Conf ] ShengYu Shen , Ying Qin , Sikun Li Localizing Errors in Counterexample with Iteratively Witness Searching. [Citation Graph (0, 0)][DBLP ] Conf ] Anyi Chen , Jian-Ming Wang , Chiu-Han Hsiao Verification of WCDMA Protocols and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung Lee , Pen-Ho Yu Efficient Representation of Algebraic Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Hyun Kim , Su-Young Lee , Young Ah Ahn , Jae-Hwan Sim , Jin Seok Yang , Na-Young Lee , Jin-Young Choi Development of RTOS for PLC Using Formal Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Liu , Jonathan Billington Reducing Parametric Automata: A Multimedia Protocol Service Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Bherer , Jules Desharnais , Marc Frappier , Richard St.-Denis Synthesis of State Feedback Controllers for Parameterized Discrete Event Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gihwon Kwon , TaeHoon Lee Solving Box-Pushing Games via Model Checking with Optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Tun Li , Yang Guo , Sikun Li CLP Based Static Property Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Hui Chang , Wei-Ting Tu , Yi-Jong Yeh , Sy-Yen Kuo A Temporal Assertion Extension to Verilog. [Citation Graph (0, 0)][DBLP ] Conf ] 