Conferences in DBLP
Randal E. Bryant Formal Verification of Pipelined Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Xinxin Liu , C. R. Ramakrishnan , Scott A. Smolka Fully Local and Efficient Evaluation of Alternating Fixed Points (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Karen Laster , Orna Grumberg Modular Model Checking of Software. [Citation Graph (0, 0)][DBLP ] Conf ] Michaela Huhn , Peter Niebert , Frank Wallner Verification Based on Local States. [Citation Graph (0, 0)][DBLP ] Conf ] Khalil Ajami , Serge Haddad , Jean-Michel Ilié Exploiting Symmetry in Linear Time Temporal Logic Model Checking: One Step Beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Hubert Garavel OPEN/CÆSAR: An OPen Software Architecture for Verification, Simulation, and Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Perdita Stevens , Colin Stirling Practical Model-Checking Using Games. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Grahlmann Combining Finite Automata, Parallel Programs and SDL Using Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Hanêne Ben-Abdallah , Stefan Leue MESA: Support for Scenario-Based Design of Concurrent Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev , Randal E. Bryant Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Pnueli , Michael Siegel , Eli Singerman Translation Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Sprenger A Verified Model Checker for the Modal µ-calculus in Coq. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Aiken , Manuel Fähndrich , Zhendong Su Detecting Races in Relay Ladder Logic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Jørn Lind-Nielsen , Henrik Reif Andersen , Gerd Behrmann , Henrik Hulgaard , Kåre J. Kristoffersen , Kim Guldstrand Larsen Verification of Large State/Event Systems Using Compositionality and Dependency Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Udo Brockmeyer , Gunnar Wittich Tamagotchis Need Not Die - Verification of STATEMENT Design. [Citation Graph (0, 0)][DBLP ] Conf ] Thierry Cattel Modeling and Verification of SC++ Applications. [Citation Graph (0, 0)][DBLP ] Conf ] David James Sherman , Nicolas Magnier Factotum: Automatic and Systematic Sharing Support for Systems Analyzers. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Aceto , Augusto Burgueño , Kim Guldstrand Larsen Model Checking via Reachability Testing for Timed Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Magnus Lindahl , Paul Pettersson , Wang Yi Formal Design and Analysis of a Gear Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Parosh Aziz Abdulla , Bengt Jonsson Verifying Networks of Timed Processes (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Conrado Daws , Stavros Tripakis Model Checking of Real-Time Reachability Properties Using Abstractions. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Alur , Thomas A. Henzinger , Sriram K. Rajamani Symbolic Exploration of transition Hierarchies. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Kurshan , Vladimir Levin , Marius Minea , Doron Peled , Hüsnü Yenigün Static Partial Order Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Witold Charatonik , Andreas Podelski Set-Based Analysis of Reactive Infinite-State Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaj Bjørner , Mark C. Pichora Deiding Fixed and Non-fixed Size Bit-vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Theo C. Ruys , Ed Brinksma Experience with Literate Programming in the Modelling and Validation of Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Ejersbo Jensen , Nancy A. Lynch A Proof of Burns N -Process Mutual Exclusion Algorithm Using Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] E. Pascal Gribomont , Guy Zenner Automated Verification of Szymanski's Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Franz Regensburger , Aenne Barnard Formal Verification of SDL Systems at the Siemens Mobile Phone Department. [Citation Graph (0, 0)][DBLP ] Conf ] 