Conferences in DBLP

Timing Issues In The Specification And Synthesis Of Digital Systems (tau)
2002 (conf/tau/2002)

1. Louis Scheffer
   Explicit computation of performance as a function of process variation. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:1-8 [Conf]
   
2. Joni Dambre, Dirk Stroobandt, Jan Van Campenhout
   A probabilistic approach to clock cycle prediction. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:9-15 [Conf]
   
3. Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
   Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:16-21 [Conf]
   
4. Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal
   Worst case clock skew under power supply variations. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:22-28 [Conf]
   
5. Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
   Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:29-36 [Conf]
   
6. Kurt Keutzer, Michael Orshansky
   From blind certainty to informed uncertainty. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:37-41 [Conf]
   
7. Avi Efrati, Moshe Kleyner
   Timing analysis challenges for high speed CPUs at 90nm and below. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:42- [Conf]
   
8. Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer
   Minimum-power retiming for dual-supply CMOS circuits. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:43-49 [Conf]
   
9. Ali Dasdan
   Efficient algorithms for debugging timing constraint violations. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:50-56 [Conf]
   
10. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    PERI: a technique for extending delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:57-62 [Conf]
    
11. Kanak Agarwal, Dennis Sylvester, David Blaauw
    A library compatible driving point model for on-chip RLC interconnects. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:63-69 [Conf]
    
12. Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang
    Aggressive crunching of extracted RC netlists. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:70-77 [Conf]
    
13. Hai Zhou
    Clock schedule verification with crosstalk. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:78-83 [Conf]
    
14. Bhavana Thudi, David Blaauw
    Efficient switching window computation for cross-talk noise. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:84-91 [Conf]
    
15. Jun Chen, Lei He
    Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:92-97 [Conf]
    
16. Himanshu Kaul, Dennis Sylvester, David Blaauw
    Active shielding of RLC global interconnects. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:98-104 [Conf]
    
17. Brian A. Floyd, Xiaoling Guo, James Caserta, Timothy O. Dickson, Chih-Ming Hung, Kihong Kim, K. O. Kenneth
    Wireless interconnects for clock distribution. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:105-108 [Conf]
    
18. Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu
    Test structures for delay variability. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:109- [Conf]
    
19. Baris Taskin, Ivan S. Kourtev
    Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:111-118 [Conf]
    
20. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
    Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:119-125 [Conf]
    
21. Paul I. Pénzes, Mika Nyström, Alain J. Martin
    Transistor sizing of energy-delay--efficient circuits. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:126-133 [Conf]
    
22. Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga
    The statistical longest path problem and its application to delay analysis of logical circuits. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:134-139 [Conf]
    
23. Sangyun Kim, Sunan Tugsinavisut, Peter A. Beerel
    Reducing probabilistic timed petri nets for asynchronous architectural analysis. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:140-147 [Conf]