Conferences in DBLP

Theorem Provers in Circuit Design (TPCD) (tpcd)
1994 (conf/tpcd/1994)

1. Thomas Kropf
   Benchmark-Circuits for Hardware-Verification. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:1-12 [Conf]
   
2. Mark Aagaard, Miriam Leeser
   Reasoning About Pipelines with Structural Hazards. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:13-32 [Conf]
   
3. Phillip J. Windley, Michael L. Coe
   A Correctness Model for Pipelined Multiprocessors. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:33-51 [Conf]
   
4. John W. O'Leary, Miriam Leeser, Jason Hickey, Mark Aagaard
   Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:52-71 [Conf]
   
5. Laurence Pierre
   An Automatic Generalization Method for the Inductive Proof of Replicated and Parallel Architectures. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:72-91 [Conf]
   
6. Zheng Zhu
   A Compositional Circuit Model and Verification by Composition. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:92-109 [Conf]
   
7. C. A. J. van Eijk, Geert Janssen
   Exploiting Structural Similarities in a BDD-Based Verification Method. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:110-125 [Conf]
   
8. Steven D. Johnson, Paul S. Miner, Albert John Camilleri
   Studies of the Single Pulser in Various Reasoning Systems. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:126-145 [Conf]
   
9. Michael Kishnievsky, Jørgen Staunstrup
   Mechanized Verification of Speed-independence. [Citation Graph (0, 0)][DBLP]
   TPCD, 1994, pp:146-164 [Conf]
   
10. Junji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi
    Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:165-184 [Conf]
    
11. Niels Maretti
    Mechanized Verification of Refinement. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:185-202 [Conf]
    
12. David Cyrluk, S. Rajan, Natarajan Shankar, Mandayam K. Srivas
    Effective Theorem Proving for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:203-222 [Conf]
    
13. Thomas Kropf, Klaus Schneider, Ramayya Kumar
    A Formal Framework for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:223-238 [Conf]
    
14. Niels Mellergaard, Jørgen Staunstrup
    Tutorial on Design Verification with Synchronized Transitions. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:239-257 [Conf]
    
15. Sam Owre, John M. Rushby, Natarajan Shankar, Mandayam K. Srivas
    A Tutorial on Using PVS for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:258-279 [Conf]
    
16. Holger Busch
    A Reduced Instruction Set Proof Environment. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:280-285 [Conf]
    
17. G. Bezzi, Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Giuseppe Zaza
    Quantitative Evaluation of Formal Based Synthesis in ASIC Design. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:286-291 [Conf]
    
18. Michel Allemand
    Formal Verification of Characteristic Properties. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:292-297 [Conf]
    
19. Kathi Fisler
    Extending Formal Reasoning with Support for Hardware Diagrams. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:298-303 [Conf]