Conferences in DBLP
Gianfranco Bilardi , Franco P. Preparata Digital Filtering in VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] David P. Helmbold , Ernst W. Mayr Two Processor Scheduling is in NC. [Citation Graph (0, 0)][DBLP ] Conf ] Greg N. Frederickson , Nicola Santoro Breaking Symmetry in Synchronous Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Yael Maon , Baruch Schieber , Uzi Vishkin Parallel Ear Decomposition Search (EDS) and St-Numbering in Graphs (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Concettina Guerra A Unifying Framework for Systolic Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Alok Aggarwal , S. Rao Kosaraju Optimal Tradeoffs for Addition on Systolic Arrays (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Günter Rote On the Connection Between Hexagonal and Unidirectional Rectangular Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Kunde Lower Bounds for Sorting on Mesh-Connected Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Arnold L. Rosenberg Diogenes, Circa 1986. [Citation Graph (0, 0)][DBLP ] Conf ] Paul M. B. Vitányi Nonsequentail Computation and Laws of Nature. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Müller , Thomas Lengauer Linear Algorithms For Two CMOS Layout Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Lodi , Linda Pagli Some New Results on a Restricted Channel Routing Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Antonis M. Paschalis , Dimitris Nikolos , Constantine Halatsis Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. [Citation Graph (0, 0)][DBLP ] Conf ] I-Chang Jou , Yu Hen Hu , T. M. Parng VLSI Algorithms and Pipelined Architectures for Solving Structured Linear System. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Kanopoulos , Peter N. Marinos A High-Performance Single-Chip VLSI Signal Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Lengauer Exploiting Hierarchy in VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Lefteris M. Kirousis A Polynomial Algorithm for Recognizing Images of Polyhedra. [Citation Graph (0, 0)][DBLP ] Conf ] Eliezer Dekel , Simeon C. Ntafos , Shietung Peng Parallel Tree Techniques and Code Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Fürer , Kurt Mehlhorn AT2 -Optimal Galois Field Multiplier for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Mihalis Yannakakis Linear and Book Embeddings of Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Gary L. Miller , Vijaya Ramachandran , Erich Kaltofen Efficient Parallel Evaluation of Straight-line Code and Arithmetric Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dario Bini , Victor Y. Pan A Logarithmic Boolean Time Algorithm for Parallel Polynomial Division. [Citation Graph (0, 0)][DBLP ] Conf ] Zevi Miller , Ivan Hal Sudborough A Polynomial Algorithm for Recognizing Samll Cutwidth in Hypergraphs. [Citation Graph (0, 0)][DBLP ] Conf ] Torben Hagerup , Wolfgang Rülling A Generalized Topological Sorting Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz A. Brzozowski , Michael Yoeli Combinatorial Static CMOD Networks (Extended Summary). [Citation Graph (0, 0)][DBLP ] Conf ] Victor Y. Pan , John H. Reif Fast and Efficient Parallel Linear Programming and Linear Least Squares Computations. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Parberry On the Time Required to Sum n Semigroup Elements on a Parallel Machine with Simultaneous Writes. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandros Biliris A Comparative Study of Concurrency Control Methods in B-Trees. [Citation Graph (1, 0)][DBLP ] Conf ] Jean R. S. Blair , Errol L. Lloyd Generalized River Routing - Algorithms and Performance Bounds (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] 