Journals in DBLP

IEEE Design & Test of Computers
2005, volume: 22, number: 6

1. Rajesh K. Gupta
   Going 3D: Silicon and D&T. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:493-494 [Journal]
   
2. Sachin S. Sapatnekar, Kevin J. Nowka
   Guest Editors' Introduction: New Dimensions in 3D Integration. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:496-497 [Journal]
   
3. W. Rhett Davis, John Wilson, Stephen Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael Steer, Paul D. Franzon
   Demystifying 3D ICs: The Pros and Cons of Going Vertical. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:498-510 [Journal]
   
4. Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher
   3D Chip Stack Technology Using Through-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:512-518 [Journal]
   
5. Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar
   Placement and Routing in 3D Integrated Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:520-531 [Journal]
   
6. Sung Kyu Lim
   Physical Design for 3D System on Package. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:532-539 [Journal]
   
7. Philip Jacob, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald
   Predicting the Performance of a 3D Processor-Memory Chip Stack. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:540-547 [Journal]
   
8. Annie (Yujuan) Zeng, James (JianQiang) Lü, Kenneth Rose, Ronald J. Gutmann
   First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:548-555 [Journal]
   
9. Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari
   Bridging the Processor-Memory Performance Gapwith 3D IC Technology. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:6, pp:556-564 [Journal]
   
10. Scott Davidson
    Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:565- [Journal]
    
11. Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil
    X-Tolerant Test Response Compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:566-574 [Journal]
    
12. Xiao Liu, Michael S. Hsiao
    A Novel Transition Fault ATPG That Reduces Yield Loss. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:576-584 [Journal]
    
13. Sagar S. Sabade, Duncan M. Walker
    IC Outlier Identification Using Multiple Test Metrics. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:586-595 [Journal]
    
14. Sachin S. Sapatnekar
    Designing "Vary" Good Circuitry. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:596-597 [Journal]
    
15. 
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:598-599 [Journal]
    
16. Vladimir Hahanov
    2005 IEEE East-West Design and Test Workshop. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:600- [Journal]
    
17. 
    Test Technology TC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:602-603 [Journal]
    
18. Robert C. Aitken
    ITC is Cool. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:616- [Journal]